Method of manufacturing a semiconductor memory using dummy source/drain contacting method

Claim 1

A method of manufacturing a semiconductor memory, comprising the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer except a portion where a contact hole is to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and a pattern film for forming the contact hole over the entire surface again; and v) removing the insulating film, the remaining conductive layer and the layer insulating film by etching one after another to form the contact hole extending to the diffused region in self-alignment.

Claim 2

A method of manufacturing a semiconductor memory, comprising the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer except a portion where a contact hole is to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and a pattern film for forming the contact hole over the entire surface again; and v) removing the insulating film, the remaining conductive layer and the layer insulating film by etching one after another to form the contact hole extending to the diffused region in self-alignment.

Claim 4

A method of manufacturing a semiconductor memory, comprising the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer except a portion where a contact hole is to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and a pattern film for forming the contact hole over the entire surface again; v) removing the insulating film, the remaining conductive layer and the layer insulating film by ethcing one after another to form the contact hole extending to the diffused region in self-alignment; vi) depositing a polysilicon film doped with impurity at high concentration and patterning the polysilicon film by projection and exposure, and reactive ion etching to form a capacitor lower electrode; and vii) further depositing a polysilicon film doped with the impurity at high concentration through a capacitor insulating film of a SiN film and patterning the polysilicon film by projection and exposure, and reactive ion etching to form a capacitor upper electrode.

Claim 5

A method of manufacturing a semiconductor memory, comprising the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer except a portion where a contact hole is to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and a pattern film for forming the contact hole over the entire surface again; v) removing the insulating film, the remaining conductive layer and the layer insulating film by ethcing one after another to form the contact hole extending to the diffused region in self-alignment; vi) depositing a polysilicon film doped with impurity at high concentration and patterning the polysilicon film by projection and exposure, and reactive ion etching to form a capacitor lower electrode; and vii) further depositing a polysilicon film doped with the impurity at high concentration through a capacitor insulating film of a SiN film and patterning the polysilicon film by projection and exposure, and reactive ion etching to form a capacitor upper electrode.

Claim 7

A method of manufacturing a semiconductor memory, comprising the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) etching the layer insulating film with a pattern film for forming a contact hole to form the contact hole extending to the diffused region in self-alignment; iii) depositing a conductive layer of a material etched more easily than the layer insulating film over the entire surface of the layer insulating film having the contact hole; iv) removing the conductive layer except the portion where the contact hole is to be formed in the diffused region, by etching with a pattern film for forming a contact hole so as to fill the contact hole with the remaining conductive layer which is to serve as a buried film; and v) depositing an insulating film over the entire surface and forming a through-hole for connecting bit line on the buried film in the insulating film to connect the bit line through the through-hole and the buried film to the diffused region.

Claim 8

A method of manufacturing a semiconductor memory, comprising the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) etching the layer insulating film with a pattern film for forming a contact hole to form the contact hole extending to the diffused region in self-alignment; iii) depositing a conductive layer of a material etched more easily than the layer insulating film over the entire surface of the layer insulating film having the contact hole; iv) removing the conductive layer except the portion where the contact hole is to be formed in the diffused region, by etching with a pattern film for forming a contact hole so as to fill the contact hole with the remaining conductive layer which is to serve as a buried film; and v) depositing an insulating film over the entire surface and forming a through-hole for connecting bit line on the buried film in the insulating film to connect the bit line through the through-hole and the buried film to the diffused region.

Claim 9

A method of manufacturing a semiconductor memory, comprising the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer except portions where contact holes for a capacitor electrode and bit line are to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and then etching back the insulating film to leave the insulating film only on the wall close to the remaining conductive layer; v) removing the remaining conductive layer by etching; and vi) etching back the layer insulating film to form a contact hole in self-alignment.

Claim 10

A method of manufacturing a semiconductor memory, comprising the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer except portions where contact holes for a capacitor electrode and bit line are to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and then etching back the insulating film to leave the insulating film only on the wall close to the remaining conductive layer; v) removing the remaining conductive layer by etching; and vi) etching back the layer insulating film to form a contact hole in self-alignment.

Claim 12

A method of manufacturing a semiconductor memory, comprising the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer except portions where contact holes for a capacitor electrode and bit line are to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and then etching back the insulating film to leave the insulating film only on the wall close to the remaining conductive layer; v) removing the remaining conductive layer by etching; vi) etching back the layer insulating film to form a contact hole in self-alignment; and vii) depositing a polysilicon film doped with impurity at high concentration over the contact hole and etching back it to form in advance a buried layer of polysilicon in the contact hole making a contact with overlayer wiring.

Claim 13

A method of manufacturing a semiconductor memory, comprising the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer except portions where contact holes for a capacitor electrode and bit line are to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and then etching back the insulating film to leave the insulating film only on the wall close to the remaining conductive layer; v) removing the remaining conductive layer by etching; vi) etching back the layer insulating film to form a contact hole in self-alignment; and vii) depositing a polysilicon film doped with impurity at high concentration over the contact hole and etching back it to form in advance a buried layer of polysilicon in the contact hole making a contact with overlayer wiring.