US4977105A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing interconnection structure in semiconductor device
Assignee: Mitsubishi Electric Corp
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Filing: 1989-08-09
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Granted: 1990-12-11
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Expires: 2009-08-09
Abstract
Abstract Conductive layers (5a, 8a) included in a multi-layer structure (30a) are electrically interconnected through an conductive connection wall (13a) provided in a contact hole (12) and contacting the side surface (22) of the multi-layer structure (30a). The upper conductive layer (11a) existing on the multi-layer structure (30a) and the lower conductive layer (3) existing under the multi-layer structure (30a) are electrically interconnected through a conductive film (11b) provided in the contact hole (12). These two interconnections are insulated from each other by an insulating film (18) provided on the connection wall (13a).
Inventors
- 👤 Tatsuo Okamoto
- 👤 Hideo Kotani
- 👤 Takio Oono
- 👤 Kiyoto Watabe
- 👤 Yasushi Kinoshita
- 👤 Yoshikazu Nishikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:38
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/083; H10W20/40; H10W20/41; H10W20/42
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
327 words
A method for manufacturing an interconnection structure interconnecting conductive layers provided in a semiconductor substrate, said method comprising the process steps of: (a) providing a first conductive layer on an upper surface of a substrate, said first conductive layer is connected to an internal circuit formed in arbitrary region on said substrate; (b) forming a first insulating layer on an upper surface of said first conductive layer; (c) providing a multi-layer structure on an upper surface of said first insulating layer, said multi-layer structure having: second conductive layers provided in parallel to said upper surface of said substrate and connected respectively to internal circuits formed in an arbitrary region on said substrate, at least one second insulating layer inserted between said second conductive layers for insulating said second conductive layers from each other, and a third insulating layer provided in a top of said multi-layer structure; (d) selectively removing said multi-layer structure to form a recess in said multi-layer structure, said recess reaching said upper surface of said first insulating layer; (e) forming a side wall covering a side surface of said multi-layer structure which defines a side surface of said recess, where said side wall includes an insulating film existing at least in a surface region of said side wall facing a center of said recess, and said side wall also contacts an outer part of a bottom surface of said recess which is a part of said upper surface of said first insulating layer; (f) selectively removing a part of said first insulating layer existing under said recess to expose a contact region being a part of said first conductive layer: and (g) forming a third conductive layer in said recess and on an upper surface of said third insulating layer, thereby to interconnect said first conductive layer and an internal circuit provided in an arbitrary region on said substrate which is connected to said third conductive layer at a place out of said recess.
Claim 2
Independent Claim
327 words
A method for manufacturing an interconnection structure interconnecting conductive layers provided in a semiconductor substrate, said method comprising the process steps of: (a) providing a first conductive layer on an upper surface of a substrate, said first conductive layer is connected to an internal circuit formed in arbitrary region on said substrate; (b) forming a first insulating layer on an upper surface of said first conductive layer; (c) providing a multi-layer structure on an upper surface of said first insulating layer, said multi-layer structure having: second conductive layers provided in parallel to said upper surface of said substrate and connected respectively to internal circuits formed in an arbitrary region on said substrate, at least one second insulating layer inserted between said second conductive layers for insulating said second conductive layers from each other, and a third insulating layer provided in a top of said multi-layer structure; (d) selectively removing said multi-layer structure to form a recess in said multi-layer structure, said recess reaching said upper surface of said first insulating layer; (e) forming a side wall covering a side surface of said multi-layer structure which defines a side surface of said recess, where said side wall includes an insulating film existing at least in a surface region of said side wall facing a center of said recess, and said side wall also contacts an outer part of a bottom surface of said recess which is a part of said upper surface of said first insulating layer; (f) selectively removing a part of said first insulating layer existing under said recess to expose a contact region being a part of said first conductive layer: and (g) forming a third conductive layer in said recess and on an upper surface of said third insulating layer, thereby to interconnect said first conductive layer and an internal circuit provided in an arbitrary region on said substrate which is connected to said third conductive layer at a place out of said recess.
Claim 3
Dependent Claim
121 words
A method in accordance with claim 1, wherein said process step (e) have the process steps of: (e-1) providing a conductive material layer in said recess and on an upper surface of said third insulating layer, said conductive material layer having an upper surface caving in said recess; (e-2) selectively etching said conductive material layer to form a conductive wall contacting only both said side surface of said multi-layer structure and said outer part of said bottom surface; and, (e-3) forming said insulating film on said surface region of said conductive wall thereby to obtain said side wall having said insulating film and said conductive wall as a connection wall for electrically interconnecting said second conductive layers in a vertical direction.
Claim 4
Dependent Claim
38 words
A method in accordance with claim 2, wherein said process step (e-2) is performed by an anistotropic etching of said conductive material layer whose etching rate in a vertical direction is greater than that in a lateral direction.
Claim 5
Dependent Claim
117 words
A method in accordance with claim 1, wherein said conductive material layer is made of silicon, a whole region of said side wall is provided as said insulating film, and said step (e) have the steps of: (e-11) providing a conductive material layer in said recess and on an upper surface of said third insulating layer, said conductive material layer having an upper surface caving in said recess; (e-12) selectively etching said conductive material layer to form a conductive wall contacting only both said side surface of said multi-layer structure and said outer part of said bottom surface; and (e-13) transforming a whole region of said conductive wall to said insulating film by oxiding said conductive wall.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-10 | 1994-06-11 | 1994-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-10 | 1998-06-11 | 1998-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-10 | 2002-06-11 | 2002-12-11 | $7700.00 | Window Closed / Lapsed |