Patent US5079441A successfully refreshed from Google Patents.
US5079441A
Expired / Lapsed
US
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Integrated circuit having an internal reference circuit to supply internal logic circuits with a reduced voltage
Assignee: Texas Instruments Inc
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Filing: 1988-12-19
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Granted: 1992-01-07
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Expires: 2008-12-19
Abstract
Abstract A bipolar/CMOS integrated circuit uses an on-chip amplifier to provide an intermediate voltage supply (18) to two groups of small geometry CMOS circuits. Bipolar devices (24) may use a full five volts from the outside supply rails (12, 14).
Inventors
- 👤 David B. Scott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:36
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/147; H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016; H10; H10D; H10D84/00; H10D84/40; H10D84/401
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
126 words
An integrated circuit including a plurality of circuits comprising: a first supply rail at a first predetermined voltage; a second supply rail at a second predetermined voltage; an intermediate supply rail at an intermediate voltage between said first and second predetermined voltages; an amplifier connected between said first and second supply rails for supplying current to said intermediate supply rail to maintain the voltage thereon at said intermediate voltage; a first logic circuit connected and biased between said first supply rail and said intermediate supply rail, wherein said first logic circuit comprises an input and an output; and a second logic circuit connected and biased between said intermediate supply rail and said second supply rail, wherein said second logic circuit comprises an input and an output.
Claim 2
Dependent Claim
126 words
An integrated circuit including a plurality of circuits comprising: a first supply rail at a first predetermined voltage; a second supply rail at a second predetermined voltage; an intermediate supply rail at an intermediate voltage between said first and second predetermined voltages; an amplifier connected between said first and second supply rails for supplying current to said intermediate supply rail to maintain the voltage thereon at said intermediate voltage; a first logic circuit connected and biased between said first supply rail and said intermediate supply rail, wherein said first logic circuit comprises an input and an output; and a second logic circuit connected and biased between said intermediate supply rail and said second supply rail, wherein said second logic circuit comprises an input and an output.
Claim 3
Dependent Claim
37 words
The integrated circuit of claim 1 wherein said first supply rail is connected to ground, said second supply rail supplies a voltage of 5 volts above ground, and said intermediate supply rail supplies 2.5 volts above ground.
Claim 4
Dependent Claim
19 words
The integrated circuit of claim 1 wherein said first and second logic circuits each comprise a plurality of circuits.
Claim 5
Dependent Claim
24 words
The integrated circuit of claim 1 further comprising a third circuit connected and biased between said first supply rail and said second supply rail.
Claim 6
Dependent Claim
19 words
The integrated circuit of claim 3 wherein said first and second logic circuits each comprise NMOS and PMOS transistors.
Claim 7
Dependent Claim
28 words
The integrated circuit of claim 5 wherein said PMOS transistors in said first logic circuit have a separate P-well from the PMOS transistors in said second logic circuit.
Claim 8
Dependent Claim
19 words
The integrated circuit of claim 5 and further comprising bipolar devices connected between said first and second supply rails.
Claim 9
Dependent Claim
40 words
The integrated circuit of claim 5 wherein the threshold voltages of the NMOS transistors of said first logic circuit have different threshold voltage adjustments than the NMOS transistors of said second logic circuit in order to compensate for backgate bias.
Claim 10
Dependent Claim
30 words
The integrated circuit of claim 5 wherein the NMOS transistors for the first logic circuit are isolated in a separate P-well from the NMOS transistors in the second logic circuit.
Claim 11
Independent Claim
92 words
A method of supplying voltage to a plurality of circuit blocks on an integrated circuit comprising the steps of: applying a first predetermined voltage across a first circuit block having an input and an output; applying a second predetermined voltage across a second circuit block having an input and an output; and providing an intermediate supply rail between said first and second circuit blocks such that said intermediate supply rail provides the low voltage supply rail for the first circuit block and the high voltage supply rial for the second circuit block.
Claim 12
Independent Claim
92 words
A method of supplying voltage to a plurality of circuit blocks on an integrated circuit comprising the steps of: applying a first predetermined voltage across a first circuit block having an input and an output; applying a second predetermined voltage across a second circuit block having an input and an output; and providing an intermediate supply rail between said first and second circuit blocks such that said intermediate supply rail provides the low voltage supply rail for the first circuit block and the high voltage supply rial for the second circuit block.
Claim 13
Dependent Claim
15 words
The method of claim 10 wherein said first predetermined voltage equals said second predetermined voltage.
Claim 14
Dependent Claim
21 words
The method of claim 10 wherein said circuits in the circuit blocks comprise CMOS circuits comprising NMOS and a PMOS transistors.
Claim 15
Dependent Claim
27 words
The method of claim 12 and further comprising the step of providing different threshold voltages for the NMOS transistors in each circuit to compensate for backgate bias.
Claim 16
Dependent Claim
22 words
The method of claim 12 and further comprising the step of providing a separate P-well for the NMOS transistors in each circuit.
Claim 17
Dependent Claim
10 words
An integrated circuit formed by the process of claim 10.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-06 | 1995-07-08 | 1996-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-06 | 1999-07-08 | 2000-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-06 | 2003-07-08 | 2004-01-07 | $7700.00 | Window Closed / Lapsed |