Circuit arrangement for producing a fluctuation-free d-c voltage level of a d-c voltage

Claim 1

Circuit arrangement for producing a fluctuation-free d-c voltage level from a fluctuating d-c supply voltage, comprising a first and a second circuit stage, the first circuit stage acting as a voltage divider having a first plurality of series connected MOS-transistors, each transistor therein having its gate connected to its drain, said first plurality of MOS-transistors being connected between the supply voltage and a frame reference potential and including a first part, a second part and a tap between said first and second parts, the second part including at least one of said first plurality of MOS-transistors and being disposed between the fluctuating supply voltage and the tap, the first part including the remainder of said first plurality of MOS-transistors and being disposed between the tap and the frame reference potential, the tap serving for supplying a tap reference potential; said second circuit stage including a second plurality of MOS-transistors located between the d-c supply voltage and said frame reference potential, the second plurality of MOS-transistors including at least a first MOS-transistor connected with its drain to the d-c supply voltage, a second MOS-transistor connected with its source to the frame reference potential and a middle MOS-transistor disposed between said first and second MOS-transistors, the first and second MOS-transistors being connected with their gates to said tap reference potential and said middle MOS-transistor being connected with its gate to the d-c supply voltage; said remainder of said first plurality of MOS-transistors including at least four of said MOS-transistors; the connection between said first MOS-transistor of said second circuit stage and said middle transistor forming the output of the circuit arrangement and producing the fluctuation-free d-c voltage level.