Voltage dividing circuit in IC structure

Claim 2

A voltage dividing circuit in IC structure for dividing DC power source voltages comprising a plurality of series-connected insulated gate FETs formed in individual substrate regions isolated from one another in a semiconductor wafer, each of said FETs having its gate short-circuited with its drain and having its source short-circuited with its substrate region wherein uniform divided DC power voltage is derived from a junction between two adjacent FETs, said uniform divided DC voltage being determined by equivalent resistance ratio of said series-connected FETs.

Claim 3

A voltage dividing circuit for dividing DC power source voltages comprising a semiconductor wafer of a first conductivity type having a major surface, a plurality of substrate regions of a second conductivity type formed in the major surface of said wafer, a drain region and a source region formed in each of said substrate region, and a gate conductor formed between the drain and source regions with an insulating film between each substrate region and the said gate conductor, thereby constituting a plurality of insulated-gate FETs in said wafer, said FETS being electrically connected in series, each of said FETs having its gate conductor short-circuited with its drain region and having its source region short-circuited with its substrate region, wherein the drain region of the FET at one end of said series-connected FETs is connected to a power source terminal, the source region of the FET at the other end of said series-connected FETs is connected to a reference potential terminal, and an output terminal is connected to a juncture between two adjacent FETs, and wherein a uniform divided DC voltage is obtained at said output terminal, said uniform divided DC voltage being exclusively determined by equivalent resistance ratio of said series-connected FETs.

Claim 4

A voltage dividing circuit for dividing DC power source voltages comprising a semiconductor wafer of a first conductivity type having a major surface, a plurality of substrate regions of a second conductivity type formed in the major surface of said wafer, a drain region and a source region formed in each of said substrate region, and a gate conductor formed between the drain and source regions with an insulating film between each substrate region and the said gate conductor, thereby constituting a plurality of insulated-gate FETs in said wafer, said FETS being electrically connected in series, each of said FETs having its gate conductor short-circuited with its drain region and having its source region short-circuited with its substrate region, wherein the drain region of the FET at one end of said series-connected FETs is connected to a power source terminal, the source region of the FET at the other end of said series-connected FETs is connected to a reference potential terminal, and an output terminal is connected to a juncture between two adjacent FETs, and wherein a uniform divided DC voltage is obtained at said output terminal, said uniform divided DC voltage being exclusively determined by equivalent resistance ratio of said series-connected FETs.

Claim 5

A voltage dividing circuit for dividing DC power source voltages comprising: a plurality N of impedance elements connected in series between first and second terminals, wherein each of said impedance elements comprises a field-effect transistor having a source and a substrate connected in common with each other, and a gate and a drain connected in common with each other, and at least one output terminal being connected to a predetermined juncture between two adjacent impedance elements, wherein a divided voltage having a uniform DC voltage is obtained at said output terminal, said divided voltage being exclusively determined by equivalent resistance ratio of said series-connected impedance elements.

Claim 6

A voltage dividing circuit for dividing DC power source voltages comprising: a plurality N of impedance elements connected in series between first and second terminals, wherein each of said impedance elements comprises a field-effect transistor having a source and a substrate connected in common with each other, and a gate and a drain connected in common with each other, and at least one output terminal being connected to a predetermined juncture between two adjacent impedance elements, wherein a divided voltage having a uniform DC voltage is obtained at said output terminal, said divided voltage being exclusively determined by equivalent resistance ratio of said series-connected impedance elements.

Claim 7

A voltage dividing circuit according to claim 3, wherein each of said plurality N of impedance elements comprises a respective enhancement mode field-effect transistor having a source and a substrate connected in common with each other, and a gate and a drain connected in common with each other.

Claim 8

A voltage dividing circuit according to claim 3, wherein said plurality N of impedance elements comprises first and second field-effect transistors, and wherein the commonly connected source and substrate of said first field-effect transistor are connected to said first terminal, and the commonly connected gate and drain of said second field-effect transistor are connected to said second terminal.

Claim 9

A voltage dividing circuit according to claim 5, wherein the commonly connected source and substrate of said second field-effect transistor are connected in common with the commonly connected drain and gate of said first field-effect transistor.

Claim 10

A voltage dividing circuit according to claim 3, wherein a first field-effect transistor of said plurality has its commonly connected source and substrate connected to said first terminal, and the commonly connected gate and drain of the N th field-effect transistor are connected to aid second terminal.

Claim 11

A voltage dividing circuit according to claim 7, wherein the commonly connected source and substrate of a j th field-effect transistor are connected in common to the commonly connected drain and gate of a (j-l) th field-effect transistor, where 2≦j≦N.

Claim 12

A voltage dividing circuit in a semiconductor integrated circuit structure for dividing DC power source voltages comprising a plurality of series-connected enhancement-mode insulated-gate FETs connected between a power source terminal and a reference potential terminal and formed in individual substrate regions of one conductivity type, which are individually defined by p-n junctions with a semiconductor wafer having a conductivity type opposite to said substrate regions, isolated from one another in said semiconductor wafer, each of said FETs having its gate short-circuited with its drain and having its source short-circuited with its substrate region, and an output terminal connected to at least one junction between said adjacent FETs for deriving a divided voltage having a uniform DC voltage being exclusively determined by equivalent resistance ratio of said series-connected FETs.

Claim 13

A voltage dividing circuit in a semiconductor integrated circuit structure for dividing DC power source voltages comprising a plurality of series-connected enhancement-mode insulated-gate FETs connected between a power source terminal and a reference potential terminal and formed in individual substrate regions of one conductivity type, which are individually defined by p-n junctions with a semiconductor wafer having a conductivity type opposite to said substrate regions, isolated from one another in said semiconductor wafer, each of said FETs having its gate short-circuited with its drain and having its source short-circuited with its substrate region, and an output terminal connected to at least one junction between said adjacent FETs for deriving a divided voltage having a uniform DC voltage being exclusively determined by equivalent resistance ratio of said series-connected FETs.

Claim 14

A voltage dividing circuit for dividing DC power source voltages comprising a semiconductor wafer of a first conductivity type having a major surface, a plurality of substrate regions of a second conductivity type opposite to said first conductivity type formed in the major surface of said wafer and isolated from one another by PN junctions with the adjacent semiconductor wafer, a drain region and a source region formed in each of said substrate regions, and a gate conductor formed between the drain and source regions with an insulating film between each substrate region and the said gate conductor, thereby constituting a plurality of enchancement-mode insulated-gate FETs in said wafer, and said plurality of said insulated-gate FETs being electrically connected in series between two different voltage source terminals, each of said FETs having its gate conductor short-circuited with its drain region and having its source region short-circuited with its substrate region, and an output terminal connected to at least one junction between said adjacent FETs for deriving a divided voltage having a uniform DC voltage being exclusively determined by equivalent resistance ratio of said series-connected FETs.

Claim 15

A voltage dividing circuit for dividing DC power source voltages comprising a semiconductor wafer of a first conductivity type having a major surface, a plurality of substrate regions of a second conductivity type opposite to said first conductivity type formed in the major surface of said wafer and isolated from one another by PN junctions with the adjacent semiconductor wafer, a drain region and a source region formed in each of said substrate regions, and a gate conductor formed between the drain and source regions with an insulating film between each substrate region and the said gate conductor, thereby constituting a plurality of enchancement-mode insulated-gate FETs in said wafer, and said plurality of said insulated-gate FETs being electrically connected in series between two different voltage source terminals, each of said FETs having its gate conductor short-circuited with its drain region and having its source region short-circuited with its substrate region, and an output terminal connected to at least one junction between said adjacent FETs for deriving a divided voltage having a uniform DC voltage being exclusively determined by equivalent resistance ratio of said series-connected FETs.

Claim 16

A voltage dividing circuit structure for dividing DC power source voltages comprising: a semiconductor wafer of a first conductivity type having a major surface; a plurality of well regions of a second conductivity type opposite to said first conductivity type formed in the major surface of said semiconductor wafer and electrically isolated from one another by PN junction with the adjacent semiconductor material of the wafer; a plurality of enhancement-mode insulated-gate FETs disposed in respective ones of said plural well regions, each of said FETs including spaced source and drain regions of the first conductivity type formed within the major surface of said well region, and a gate electrode separated by a gate insulator from the major surface of said well region between said source and drain regions; first conductive means for connecting the respective gate electrodes of said plural FETs to their respective drain regions; second conductive means for connecting the respective well regions to the respective source regions formed therein; third conductive means for connecting the drain region of one of said FETs to the source region of another thereof to electrically connect said plural FETs in series; a reference potential terminal connected to the source region of the FET at one end of said semiconductor FETs and a power source terminal connected to the drain region of the FET at the other end of said series-connected FETs respectively; and an output terminal connected to at least one juncture between the adjacent FETs of said series-connected FETs for deriving a divided voltage having a uniform DC voltage being exclusively determined by equivalent resistance ratio of said series-connected FETs.

Claim 17

A voltage dividing circuit structure for dividing DC power source voltages comprising: a semiconductor wafer of a first conductivity type having a major surface; a plurality of well regions of a second conductivity type opposite to said first conductivity type formed in the major surface of said semiconductor wafer and electrically isolated from one another by PN junction with the adjacent semiconductor material of the wafer; a plurality of enhancement-mode insulated-gate FETs disposed in respective ones of said plural well regions, each of said FETs including spaced source and drain regions of the first conductivity type formed within the major surface of said well region, and a gate electrode separated by a gate insulator from the major surface of said well region between said source and drain regions; first conductive means for connecting the respective gate electrodes of said plural FETs to their respective drain regions; second conductive means for connecting the respective well regions to the respective source regions formed therein; third conductive means for connecting the drain region of one of said FETs to the source region of another thereof to electrically connect said plural FETs in series; a reference potential terminal connected to the source region of the FET at one end of said semiconductor FETs and a power source terminal connected to the drain region of the FET at the other end of said series-connected FETs respectively; and an output terminal connected to at least one juncture between the adjacent FETs of said series-connected FETs for deriving a divided voltage having a uniform DC voltage being exclusively determined by equivalent resistance ratio of said series-connected FETs.

Claim 18

A voltage dividing circuit structure according to claim 11, wherein said semiconductor wafer is electrically connected to the drain region of the FET at said other end of the series-connected FETS.