Parallel string processor and method for a minicomputer

Claim 2

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit, said identified bit indicating the location of a byte in said first data word that has a selected matching or non-matching characteristic with respect to the byte in the corresponding location of said second data word.

Claim 3

The parallel byte processor as defined in claim 1, wherein said second circuit comprises a programmable read only memory.

Claim 4

The parallel byte processor as defined in claim 1, further including means to perform a multi-way conditional branch upon identifying the most significant byte of said first data word that matches the corresponding byte of said second data word.

Claim 5

The parallel byte processor as defined in claim 1, further including means to perform a multi-way conditional branch upon identifying the most significant byte of said first data word that does not match the corresponding byte of said second data word.

Claim 6

The parallel byte processor as defined in claim 1, further including means to clear the byte positions in said first data word from the location of the most significant byte of said first data word that matches the corresponding byte of said second data word to the least significant byte of said first data word.

Claim 7

The parallel byte processor as defined in claim 1, further including means to clear the byte positions of said first data word from the most significant byte of said first data word up to the location of the most significant byte of said first data word that matches the corresponding byte of said second data word.

Claim 8

The parallel byte processor as defined in claim 1, further including means to clear the most significant byte of said first data word that matches the corresponding byte of said second data word.

Claim 9

The parallel byte processor as defined in claim 1, further including means to clear the byte positions of said first data word from the location of the most significant byte of said first data word that does not match the corresponding byte of said second data word to the least significant byte of said first data word.

Claim 10

The parallel byte processor as defined in claim 1, further including means to clear the byte positions of said first data word from the most significant byte of said first data word up to the location of the most significant byte of said first data word that does not match the corresponding byte of said second data word.

Claim 11

The parallel byte processor as defined in claim 1, further including means to clear the most significant byte of said first data word that does not match the corresponding byte of said second data word.

Claim 12

The parallel byte processor as defined in claim 1, further including means to clear the output bit from said first circuit corresponding to the location of the most significant byte of said first data word that matches the corresponding byte of said second data word.

Claim 13

The parallel byte processor as defined in claim 1, further including means to clear the output bit from said first circuit corresponding to the location of the most significant byte of said first data word that does not match the corresponding byte of said second data word.

Claim 14

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit which is the location of the most significant bit of said output bits having said first logic level, thus identifying the most significant byte of said first data word that matches the corresponding byte of said second data word.

Claim 15

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit which is the location of the most significant bit of said output bits having said first logic level, thus identifying the most significant byte of said first data word that matches the corresponding byte of said second data word.

Claim 16

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit which is the location of the most significant bit of said output bits having said second logic level, thus identifying the most significant byte of said first data word that does not match the corresponding byte of said second data word.

Claim 17

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit which is the location of the most significant bit of said output bits having said second logic level, thus identifying the most significant byte of said first data word that does not match the corresponding byte of said second data word.

Claim 18

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit which is the location of the most significant bit of said output bits having said first logic level that is less significant than a bit of said output bits having said second logic level, thus identifying the most significant byte of said first data word that does not match the corresponding byte of said second data word that is less significant than a byte of said first data word that matches the corresponding byte of said second data word.

Claim 19

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit which is the location of the most significant bit of said output bits having said first logic level that is less significant than a bit of said output bits having said second logic level, thus identifying the most significant byte of said first data word that does not match the corresponding byte of said second data word that is less significant than a byte of said first data word that matches the corresponding byte of said second data word.

Claim 20

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit which is the location of the most significant bit of said output bits having said second logic level that is less significant than a bit of said output bits having said first logic level, thus identifying the most significant byte of said first data word that matches the corresponding byte of said second data word that is less significant than a byte of said first data word that does not match the corresponding byte of said second data word.

Claim 21

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit which is the location of the most significant bit of said output bits having said second logic level that is less significant than a bit of said output bits having said first logic level, thus identifying the most significant byte of said first data word that matches the corresponding byte of said second data word that is less significant than a byte of said first data word that does not match the corresponding byte of said second data word.

Claim 22

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit, said identified bit indicating the location of a byte in said first data word that has a selected matching or non-matching characteristic with respect to the byte in the corresponding location of said second data word wherein said bit having said characteristic is the first of at least two adjacent bits having said characteristic.

Claim 23

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit, said identified bit indicating the location of a byte in said first data word that has a selected matching or non-matching characteristic with respect to the byte in the corresponding location of said second data word wherein said bit having said characteristic is the first of at least two adjacent bits having said characteristic.

Claim 24

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, wherein said second data word comprises a plurality of identical bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit, said identified bit indicating the location of a byte in said first data word that has a selected matching or non-matching characteristic with respect to the byte in the corresponding location of said second data word; and a replication circuit, said replication circuit receiving a single byte input and generating said predetermined number of bytes as outputs, each of said predetermined number of bytes being identical to said input byte.

Claim 25

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, wherein said second data word comprises a plurality of identical bytes, said parallel byte processor comprising: a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word; and a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit, said identified bit indicating the location of a byte in said first data word that has a selected matching or non-matching characteristic with respect to the byte in the corresponding location of said second data word; and a replication circuit, said replication circuit receiving a single byte input and generating said predetermined number of bytes as outputs, each of said predetermined number of bytes being identical to said input byte.

Claim 26

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word having data of unknown content in said bytes and that finds the location of a byte in said first multiple-byte data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first multiple-bytes data word, comprising: a first circuit that provides an output signal for each byte of said first multiple-byte data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic; and a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first multiple-byte data word having said selected positional characteristic.

Claim 27

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word having data of unknown content in said bytes and that finds the location of a byte in said first multiple-byte data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first multiple-bytes data word, comprising: a first circuit that provides an output signal for each byte of said first multiple-byte data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic; and a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first multiple-byte data word having said selected positional characteristic.

Claim 28

The parallel byte processor as defined in claim 19, further including means to perform a multi-way conditional branch upon identifying the most significant byte of said first multiple-byte data word having said selected content characteristic.

Claim 29

The parallel byte processor as defined in claim 19, further including means to perform a multi-way conditional branch upon identifying the most significant byte of said first multiple-byte data word not having said selected content characteristic.

Claim 30

The parallel byte processor as defined in claim 19, further including means to clear the byte positions in said first multiple-byte data word from the location of the most significant byte of said first multiple-byte data word having said selected content characteristic to the least significant byte of said first multiple-byte data word.

Claim 31

The parallel byte processor as defined in claim 19, further including means to clear the byte positions of said first multiple-byte data word from the most significant byte of said first multiple-byte data word up to the location of the most significant byte of said first multiple-byte data word having said selected content characteristic.

Claim 32

The parallel byte processor as defined in claim 19, further including means to clear the most significant byte of said first multiple-byte data word having said selected content characteristic.

Claim 33

The parallel byte processor as defined in claim 19, further including means to clear the byte positions of said first multiple-type data word from the location of the most significant byte of said first multiple-byte data word not having said selected content characteristic to the least significant byte of said first multiple-byte data word.

Claim 34

The parallel byte processor as defined in claim 19, further including means to clear the byte positions of said first multiple-byte data word from the most significant byte of said first multiple-byte data word up to the location of the most significant byte of said first multiple-byte data work not having said selected content characteristic.

Claim 35

The parallel byte processor as defined in claim 19, further including means to clear the most significant byte of said first multiple-byte data word not having said selected content characteristic.

Claim 36

The parallel byte processor as defined in claim 19, further including means to clear the output bit from said first circuit corresponding to the location of the most significant byte of said first multiple-byte data word having said selected content characteristic.

Claim 37

The parallel byte processor as defined in claim 19, further including means to clear the output bit from said first circuit corresponding to the location of the most significant byte of said first multiple-byte data word not having said selected content characteristic.

Claim 38

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising: a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic; and a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, and wherein said selected content characteristic of a byte in said first data word is equal to the corresponding byte of said second data word.

Claim 39

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising: a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic; and a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, and wherein said selected content characteristic of a byte in said first data word is equal to the corresponding byte of said second data word.

Claim 40

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising: a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic; and a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, wherein said selected positional characteristic is the most significant byte having said selected content characteristic.

Claim 41

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising: a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic; and a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, wherein said selected positional characteristic is the most significant byte having said selected content characteristic.

Claim 42

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising: a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic; and a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, wherein said selected positional characteristic is the most significant byte not having said selected content characteristic.

Claim 43

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising: a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic; and a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, wherein said selected positional characteristic is the most significant byte not having said selected content characteristic.

Claim 44

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising: a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic; and a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, wherein said selected positional characteristic is the most significant byte having said selected content characteristic that is less significant than the most significant byte not having said selected content characteristic.

Claim 45

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising: a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic; and a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, wherein said selected positional characteristic is the most significant byte having said selected content characteristic that is less significant than the most significant byte not having said selected content characteristic.

Claim 46

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising: a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic; and a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, wherein said selected positional characteristic is the most significant byte not having said selected content characteristic that is less significant than the most significant byte having said selected content characteristic.

Claim 47

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising: a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic; and a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, wherein said selected positional characteristic is the most significant byte not having said selected content characteristic that is less significant than the most significant byte having said selected content characteristic.