US4414677A
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Synchronization word extractor
Assignee: Sony Corp
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Filing: 1981-11-02
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Granted: 1983-11-08
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Expires: 2001-11-02
Abstract
Abstract Apparatus for extracting synchronizing information from an incoming serial-bit digital television signal formed of a sequence of data blocks, each block formed of N n-bit words and including within each block a predetermined serial group of m bits forming the synchronizing information, which identify each block of information and enable de-serialization of said signal. The apparatus comprises a first m-stage shift register through which the incoming digital signal is stepped at the bit rate of the incoming digital signal, and which supplies a pulse whenever it holds a predetermined serial group of m bits, a frequency divider to derive from the incoming digital signal a word rate clock pulse signal. Additionally, the apparatus comprises an n-stage shift register through which each said pulse is stepped at the bit rate of the incoming digital signal, a latch circuit synchronized with the word rate clock pulse signal to derive n-bit phase words the bits of which correspond respectively to the conditions of the n stages of the shift register, comparators comparing each phase word with at least one other phase word delayed N or an integral multiple of N word periods of an earlier incoming digital signal. Comparators supply a control signal only when at least one of the comparisons indicates two phase words which are identical and both contain a bit corresponding to a said pulse, wherein the position of this bit in the phase words indicates the phasing of the word rate clock pulse signal relative to the words of the incoming digital signal. In addition, circuits are provided to deserialize the incoming digital signal into parallel-bit n-bit words under control of the control signal.
Inventors
- 👤 John G. S. Ive
- 👤 Alan C. Thirlwall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:57
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/08; G; G11; G11B; G11B20/00; G11B20/10; G11B20/12; G11B20/18; G11B20/1806; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; H04N5/935; G11B2220/00; G11B2220/90
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
290 words
Apparatus for extracting synchronizing information from an incoming serial-bit digital signal, said signal forming a sequence of data blocks each of which has N n-bit words and a predetermined serial group of m bits forming said synchronizing information, said synchronizing information identifying each block of data, the apparatus comprising: a first shift register arrangement including a first m-stage shift register through which said incoming digital signal is stepped at the bit rate of said incoming digital signal, said first shift register arrangement supplying a pulse when said first shift register holds said predetermined serial group of m bits; means to derive from said incoming digital signal a word rate clock pulse signal; a second shift register arrangement including a second n-stage shift register through which each pulse supplied by said first shift register is stepped at the bit rate of said incoming digital signal, and latch means synchronized with said word rate clock pulse signal to derive n-bit phase words, the bits of which correspond respectively to the conditions of the n stages of said second shift register; comparator means for effectively comparing each phase word with at least one other phase word delayed by N word periods or a integral multiple of N word periods of an earlier incoming digital signal; said comparator means supplying a control signal only when at least one of said comparisons indicates two phase words which are identical and both contain a bit corresponding to a said pulse, the position of said bit in said phase words indicating the phasing of said word rate clock pulse signal relative to the words of said incoming digital signals; and means to de-serialize said incoming digital signal into parallel-bit n-bit words under control of said control signal.
Claim 2
Dependent Claim
290 words
Apparatus for extracting synchronizing information from an incoming serial-bit digital signal, said signal forming a sequence of data blocks each of which has N n-bit words and a predetermined serial group of m bits forming said synchronizing information, said synchronizing information identifying each block of data, the apparatus comprising: a first shift register arrangement including a first m-stage shift register through which said incoming digital signal is stepped at the bit rate of said incoming digital signal, said first shift register arrangement supplying a pulse when said first shift register holds said predetermined serial group of m bits; means to derive from said incoming digital signal a word rate clock pulse signal; a second shift register arrangement including a second n-stage shift register through which each pulse supplied by said first shift register is stepped at the bit rate of said incoming digital signal, and latch means synchronized with said word rate clock pulse signal to derive n-bit phase words, the bits of which correspond respectively to the conditions of the n stages of said second shift register; comparator means for effectively comparing each phase word with at least one other phase word delayed by N word periods or a integral multiple of N word periods of an earlier incoming digital signal; said comparator means supplying a control signal only when at least one of said comparisons indicates two phase words which are identical and both contain a bit corresponding to a said pulse, the position of said bit in said phase words indicating the phasing of said word rate clock pulse signal relative to the words of said incoming digital signals; and means to de-serialize said incoming digital signal into parallel-bit n-bit words under control of said control signal.
Claim 3
Dependent Claim
69 words
Apparatus according to claim 1 wherein said second shift register arrangement further includes a programmable read-only memory for coding said n-bit phase words into respective binary code words each representing a decimal number indicating the position of said bit in said phase word, or if there is no said bit, the absence of any said bit in said phase word; and wherein said comparator means compares said code words.
Claim 4
Dependent Claim
51 words
Apparatus according to claim 2 wherein said comparator means comprises a plurality of comparators each able to compare two said code words and first delay means for respectively delaying a like plurality of said code words by N, 2N, 3N, . . . word periods respectively of said incoming digital signal.
Claim 5
Dependent Claim
12 words
Apparatus according to claim 3 wherein said plurality is equal to four.
Claim 6
Dependent Claim
59 words
Apparatus according to claim 3 wherein said comparator means further comprises evaluation means for evaluating the results of the comparison effected by said plurality of comparators and for supplying said control signal only when all of said comparators indicate two code words which are identical and correspond to a phase word containing a bit corresponding to a said pulse.
Claim 7
Dependent Claim
15 words
Apparatus according to claim 5 wherein said evaluation means is a further programmable read-only memory.
Claim 8
Dependent Claim
62 words
Apparatus according to claim 1 wherein said first shift register has m outputs coupled to the m stages respectively, some of said outputs being true outputs and the remainder being inverse outputs, and the arrangement being such that when said first shift register holds said predetermined serial group of m bits each one of said outputs is supplied with a similar signal.
Claim 9
Dependent Claim
28 words
Apparatus according to claim 7 wherein said outputs of said first shift register are respectively connected to the inputs of an m-input NAND gate, which supplies said pulse.
Claim 10
Dependent Claim
119 words
Apparatus according to claim 3 wherein said means to de-serialize said incoming digital signal comprises a first n-input latch circuit the inputs of which are respectively coupled to n of the m stages of said shift register where m is greater than or equal to n, second delay means coupled to the outputs of said first latch circuit for effecting a delay equal to the maximum delay of said first delay means, means for deriving from the output of said second delay means 2n-1 bits in parallel and corresponding to 2n-1 serial bits of said incoming digital signal, and means to select from said 2n-1 bits under control of said control signal the n bits forming one said word.
Claim 11
Dependent Claim
15 words
Apparatus according to claim 1 wherein said incoming digital signal is a digital television signal.
Claim 12
Dependent Claim
9 words
Apparatus according to claim 1 wherein n is ten.
Claim 13
Dependent Claim
9 words
Apparatus according to claim 11 wherein m is twelve.
Claim 14
Dependent Claim
9 words
Apparatus according to claim 12 wherein N is sixty-four.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-07 | 1987-05-09 | 1987-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-07 | 1991-05-09 | 1991-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-07 | 1995-05-09 | 1995-11-08 | $7700.00 | Window Closed / Lapsed |