Serial comparison flag detector

Claim 1

Apparatus for detecting a flag pattern in a serial sequence of digital data signals, comprising means for simultaneously providing bit signals corresponding to the bits in the flag pattern, a plurality of comparators for simultaneously comparing each data signal in its turn with all the bit signals, each comparator being adapted to compare the data signal with a different one of the bit signals and emit a set signal upon the occurrence of a match, a shift register having at least as many stages as there are bits in the flag pattern, the shift register being adapted to advance a logic signal from each set stage to the next stage in response to a clock signal, the comparator which compares the data signal with the bit signal corresponding to the first bit in the flag pattern having its output applied to the input of the first stage of the shift register, a plurality of gates, each stage of the shift register being connected to the next succeeding stage by a different one of those gates, each gate obtaining one input from the output of a corresponding one of the comparators and obtaining another input from the preceding stage of the shift register, the comparator which compares the data signal with the bit signal corresponding to the second bit in the flag pattern providing the input signal to the gate connecting the first stage of the shift register to the second stage, the comparator which compares the data signal with the bit signal corresponding to the third bit in the flag pattern providing the input signal for the gate connecting the second stage to the third stage, the other gates and comparators being arranged in like manner in consecutive order corresponding to the order of the signal bits, and each gate enabling a logic signal to be shifted from the preceding stage of the shift register to the succeeding stage only if the preceding stage was previously set and a set signal is received by the gate from its comparator.