Digital pattern detector

Claim 3

The method as recited in claim 1, wherein sampling the contents of said predetermined intermediate stages of said sample and storage means includes the steps of; determining the stage of said sample and storage means that corresponds to each bit of said predetermined pattern upon said pattern being completely loaded into said sample and storage means, the bits of said pattern filling all stages prior to the last stage thereof, and connecting comparison means to the stages of said sample and storage means that correspond to the bits of said predetermined pattern that immediately precede a transition therein.

Claim 4

The method as recited in claim 1, wherein said comparison signal is provided by the steps of: comparing the contents of said first stage of said sample and storage means with a predetermined one of said bits of said second digital pattern, providing a first sense signal when the contents of said first stage has a first predetermined relationship to said compared bit of said second pattern, and providing a null signal when the contents of said first stage has a second predetermined relationship to said compared bit of said second pattern; comparing the contents of each of said predetermined intermediate stages of said sample and storage means each with a predetermined one of the bits of said second digital pattern, each comparison providing a first sense signal when the contents of said associated intermediate stage has one of said first and second predetermined relationships to said compared bit, and providing a second sense signal when the contents of said associated intermediate stage has the other of said first and second predetermined relationships to said compared bit; comparing the contents of said last stage of said sample and storage means with a predetermined bit of said second digital pattern, providing a null signal when the contents of said last stage has one of said first and second predetermined relationships to said compared bit, and providing a second sense signal when the contents of said last stage has the other of said first and second predetermined relationships to said compared bit, wherein said first sense signals, said second sense signals and said null signals determine said comparison signal.

Claim 5

The method as recited in claim 1, wherein said comparison signal is provided by the steps of: comparing the contents of said first stage of said sample and storage means with a predetermined one of said bits of said digital pattern, and adding a unit when said contents and said bit are similar; comparing the contents of each of said predetermined intermediate stages of said sample and storage means each with a predetermined one of the bits of said second digital pattern, adding a unit for each comparison wherein said contents and said predetermined bit are similar, and subtracting a unit for each comparison wherein said contents and said predetermined bit are dissimilar; and comparing the contents of said last stage of said sample and storage means with a predetermined bit of said second digital pattern, subtracting a unit when said contents and said bit are similar, wherein said comparison signal is related to the aggregate of said units.

Claim 6

The method as recited in claim 1 wherein the second digital pattern is provided by the steps of: determining the bits contained in each of the first and sampled intermediate stages of said sample and storage means upon said predetermined pattern being completely loaded into said sample and storage means, the bits of said pattern filling all stages prior to the last stage thereof, and loading bits corresponding to said bits into a memory means; and providing a bit related to said entire predetermined pattern for negating any contribution to said count previously provided by the bit stored in the last stage of said sample and storage means, and loading a bit corresponding to said negating bit into said memory means, said loaded bits comprisIng said second digital pattern.

Claim 9

A system as recited in claim 6 wherein said comparison means is connected to the intermediate stages of said sample and storage means that correspond to bits of said predetermined pattern that immediately precede a transition therein upon said predetermined pattern being loaded into said sample and storage means and filling all stages prior to the last stage thereof.

Claim 10

A system as recited in claim 7 wherein said comparison means and said counting means include means for raising the value of the count in said counting means when the bit stored in said first stage of said sample and storage means has a first of a first and second predetermined relationship to one bit of said second digital pattern, means for raising the value of the count in said counting means for each bit stored in said predetermined intermediate stages having one of said first and second predetermined relationships to an associated bit in said second digital pattern, and for lowering the count for each bit stored in said predetermined intermediate stages having the other of said first and second relationships to an associated bit, and means for lowering the value of the count in said counting means when the bit stored in the last stage of said sample and storage means has one of said first and second predetermined relationships to one bit in said second digital pattern.

Claim 11

A system as recited in claim 8 wherein said counting means further include means for adding one to the count in said counting means when the bit stored in said first stage of said sample and storage means is similar to a predetermined bit stored in said memory means, means for adding one to the count for each bit stored in said predetermined intermediate stages that is similar to an associated bit stored in said memory means, and for substracting one for each bit that is dissimilar to an associated bit stored in said memory means, and means for subtracting one from the count when the bit stored in the last stage of said sample and storage means is similar to a compared bit stored in said memory means.

Claim 12

A system as recited in claim 8 further including means for entering bits into said memory means, each of said bits prior to a last bit being individually related to one of the first and intermediate bits of said predetermined pattern that immediately precede a transition in said pattern, the last bit entered into said memory means being related to the entire prEdetermined pattern for causing said comparison means to negate any contributions to the count in said counting means previously provided by the bit stored in the last stage of said sample and storage means.

Claim 13

A system as recited in claim 6 wherein said sample and storage means includes a shift register.

Claim 14

A system as recited in claim 6 wherein said memory means is a storage register having a plurality of stages.

Claim 15

A system as recited in claim 6 wherein said comparison means includes a plurality of gate means, each of said gate means being connected to one stage of said sample and storage means and to said memory means.

Claim 16

A system as recited in claim 6 wherein said counting means includes means for limiting the value of the count therein to the range including zero to the number of bits comprising said predetermined pattern.

Claim 17

A system as recited in claim 14 wherein said counting means includes an up-down counter.

Claim 18

A system as recited in claim 15 further including means for providing a pattern recognition signal when the count in said counting means reaches a predetermined value.

Claim 19

A system as recited in claim 6 wherein said clock means includes means for causing said sample and storage means to sample said digital signal and to shift bits previously stored therein between stages thereof, and further includes means for causing said counting means to count said comparison signals during the time interval between shifts.