US4205302A
Expired / Lapsed
US
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Word recognizing system
Assignee: Individual
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Filing: 1978-11-29
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Granted: 1980-05-27
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Expires: 1998-11-29
Abstract
Abstract A stream of digital data containing an unknown word is compared bit by bit with a stored known word. The bit comparisons are counted in such a manner that the maximum output identifies the known word in the data stream. Alternatively, the non-comparing bits may be counted so that a minimum output identifies the known word.
Inventors
- 👤 Einar Godo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:38
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/02; G06F2207/00; G06F2207/02; G06F2207/025
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
110 words
A method of recognizing a word containing a number of bits in a data stream, comprising: recirculating a known word in a first shift register clocked in a first direction; clocking said data stream through a second shift register in a direction opposite from said first direction; comparing each bit of the known word stored in a respective stage of said first shift register with a bit of said data stream stored in a corresponding stage of said second shift register; counting the number of comparing bits for each stage of registers during a plurality of clocking periods to determine if said word has been received in said data stream.
Claim 2
Independent Claim
110 words
A method of recognizing a word containing a number of bits in a data stream, comprising: recirculating a known word in a first shift register clocked in a first direction; clocking said data stream through a second shift register in a direction opposite from said first direction; comparing each bit of the known word stored in a respective stage of said first shift register with a bit of said data stream stored in a corresponding stage of said second shift register; counting the number of comparing bits for each stage of registers during a plurality of clocking periods to determine if said word has been received in said data stream.
Claim 3
Dependent Claim
78 words
The method of claim 1 further comprising: providing a signal for resetting the counter and transferring the output from the counter to an output register by a command signal from a third serial register clocked is said first direction is synchronism with said known word; clocking the contents of said output registers in a direction opposite said first direction and determining the maximum output of the output register to identify the known word in said stream of data.
Claim 4
Dependent Claim
93 words
The method of claim 1 further including: recirculating a command bit through a third shift register in said first direction in synchronism with the first bit of said word; transferring the count of matching bits for each stage of registers to responsive output registers and resetting the count for each stage to zero responsive to receipt of said command bit at each stage; and determining when the count stored in one of said output registers equals the number of bits forming said word thereby providing an indication that said word has been received.
Claim 5
Independent Claim
128 words
A method of recognizing a word formed by a number of bits in a data stream, comprising: clocking said stream of data through a shift register; storing a known word in a storage register; comparing each bit of the known word stored in a respective stage of said storage register with a bit of said data stream stored in a corresponding stage of said shift register for each clock period as said data is clocked through said shift register; counting the number of matching bits for each stage of registers in a first group during alternate clocking periods and in a second group during the remaining clock periods; and determining when the count in either the first or second group equals the number of bits forming the word.
Claim 6
Independent Claim
128 words
A method of recognizing a word formed by a number of bits in a data stream, comprising: clocking said stream of data through a shift register; storing a known word in a storage register; comparing each bit of the known word stored in a respective stage of said storage register with a bit of said data stream stored in a corresponding stage of said shift register for each clock period as said data is clocked through said shift register; counting the number of matching bits for each stage of registers in a first group during alternate clocking periods and in a second group during the remaining clock periods; and determining when the count in either the first or second group equals the number of bits forming the word.
Claim 7
Independent Claim
198 words
An apparatus for recognizing a word formed by a number of bits in a data stream comprising: a first shift register having its output connected to its input such that data stored therein may be continuously recirculated, said shift register having a number of stages equal to the number of bits forming said word with each stage containing one of said bits; a second shift register having the same number of stages as said first shift register, said second shift register receiving said data stream at its input; clock means connected to said first and second shift registers for recirculating said word through said first register and clocking said data stream through said second shift register; respective comparator means receiving the outputs of each stage of said first shift register and the corresponding stage of said second shift register; counter means receiving the outputs of said comparator means for counting the number of matching bits stored in corresponding stages of said first and second registers during a plurality of clocking periods to determine when said count equals the number of bits forming said word thereby providing an indication that said word has been received in said data stream.
Claim 8
Independent Claim
198 words
An apparatus for recognizing a word formed by a number of bits in a data stream comprising: a first shift register having its output connected to its input such that data stored therein may be continuously recirculated, said shift register having a number of stages equal to the number of bits forming said word with each stage containing one of said bits; a second shift register having the same number of stages as said first shift register, said second shift register receiving said data stream at its input; clock means connected to said first and second shift registers for recirculating said word through said first register and clocking said data stream through said second shift register; respective comparator means receiving the outputs of each stage of said first shift register and the corresponding stage of said second shift register; counter means receiving the outputs of said comparator means for counting the number of matching bits stored in corresponding stages of said first and second registers during a plurality of clocking periods to determine when said count equals the number of bits forming said word thereby providing an indication that said word has been received in said data stream.
Claim 9
Dependent Claim
200 words
The apparatus of claim 5 further including means for resetting said counters, comprising: an output register having a number of stages equal to the number of stages of said counter means with each stage receiving the output of a corresponding stage of said counter means responsive to a signal received on an output register load terminal; a third shift register having its output connected to its input and being incremented by said clock means such that data contained therein is continuously recirculated, said shift register having a number of stages equal to the number of stages of said counter with their outputs connected to the reset terminal of a corresponding stage of said counter means and to the load terminal of a corresponding stage of said output register, said third shift register containing a single bit recirculating in synchronism with the first bit of said word, said bit being capable of resetting said counter means and loading the outputs of said counter means into said output register; and means of examining the contents of said output registers for a number equal to the number of bits forming said known word thereby providing an indication that said word has been received.
Claim 10
Independent Claim
184 words
An apparatus for recognizing a word formed by a numbe of bits in a data stream, comprising: a storage register having a number of stages equal to the number of bits forming said word with each stage containing one of said bits; a shift register having the same number of stages as said storage register, said shift register receiving said data stream at its input; respective comparator means receiving the outputs of each stage of said storage register and the corresponding stage of said shaft register; clock means connected to said shift register for clocking said data stream through said shift register; first and second counter means receiving the outputs of said comparator means for counting the number of matching bits stored in corresponding stages of said storage register and said shift register during a purality of clocking periods; control means receiving the output of said clock means for alternately enabling said first and second counter means during alternate clock periods; and output means for determining when the count in either the first or second counter equals the number of bits forming the word.
Claim 11
Independent Claim
184 words
An apparatus for recognizing a word formed by a numbe of bits in a data stream, comprising: a storage register having a number of stages equal to the number of bits forming said word with each stage containing one of said bits; a shift register having the same number of stages as said storage register, said shift register receiving said data stream at its input; respective comparator means receiving the outputs of each stage of said storage register and the corresponding stage of said shaft register; clock means connected to said shift register for clocking said data stream through said shift register; first and second counter means receiving the outputs of said comparator means for counting the number of matching bits stored in corresponding stages of said storage register and said shift register during a purality of clocking periods; control means receiving the output of said clock means for alternately enabling said first and second counter means during alternate clock periods; and output means for determining when the count in either the first or second counter equals the number of bits forming the word.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-05-27 | 1983-11-26 | 1984-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-05-27 | 1987-11-26 | 1988-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-05-27 | 1991-11-26 | 1992-05-27 | $7700.00 | Window Closed / Lapsed |