Method of making a diffusionless virtual drain and source conductor/oxide semiconductor field effect transistor

Claim 1

A method for fabricating at least one diffusionless field effect transistor at a face of a semiconductor layer having a first conductivity type, comprising the steps of: forming a thin insulator layer over the face of the semiconductor layer; forming first and second diffused regions, each of a second conductivity type opposite the first conductivity type, the first diffused region formed to lie adjacent a future source conductor, the second diffused region formed to lie adjacent a future drain conductor; forming a first conductor layer over the layer of thin insulator; selectively etching the first conductor layer to define a source conductor and a drain conductor, laterally spaced apart by a channel region of the semiconductor layer; forming a first interlayer insulator, layer overlying the source and drain conductors and the channel region; forming a second conductor layer over the first interlayer insulator layer; selectively etching the source conductor layer to define a gate conductor insulatively overlying the channel region; forming a second interlayer insulator layer overlying the gate conductor; and forming a first metal contact terminating at the first diffused region and a second metal contact terminating at the second diffused region.

Claim 2

A method for fabricating at least one diffusionless field effect transistor at a face of a semiconductor layer having a first conductivity type, comprising the steps of: forming a thin insulator layer over the face of the semiconductor layer; forming first and second diffused regions, each of a second conductivity type opposite the first conductivity type, the first diffused region formed to lie adjacent a future source conductor, the second diffused region formed to lie adjacent a future drain conductor; forming a first conductor layer over the layer of thin insulator; selectively etching the first conductor layer to define a source conductor and a drain conductor, laterally spaced apart by a channel region of the semiconductor layer; forming a first interlayer insulator, layer overlying the source and drain conductors and the channel region; forming a second conductor layer over the first interlayer insulator layer; selectively etching the source conductor layer to define a gate conductor insulatively overlying the channel region; forming a second interlayer insulator layer overlying the gate conductor; and forming a first metal contact terminating at the first diffused region and a second metal contact terminating at the second diffused region.