Semiconductor ballistic electron velocity control structure

Claim 2

In a compound semiconductor structure of the type where carriers in a semiconductor crystal material are launched from an emitter for ballistic transport across a base to a collector, the improvement for controlling the kinetic energy gained by the ballistic transport carriers comprising a first barrier in said base adjacent said emitter and a planar doped type barrier in said base adjacent said collector, said first barrier and said planar doped type barrier operable to provide an essentially level conduction band profile across the base of the semiconductor structure between the two carriers under suitable bias voltages.

Claim 3

The structure of claim 1 where said base semiconductor material comprises GaAs layers and said planar doped barrier is a narrow p ++ type region.

Claim 4

In a semiconductor structure having an emitter, a base and a collector, and wherein carriers are transported under the influence of biasing voltages, the improvement comprising the combination of at least one voltage biased compositional barrier located in the base adjacent the emitter and at least one voltage biased electrostatic barrier located in the base and interposed between the compositional barrier and the collector.

Claim 5

In a semiconductor structure having an emitter, a base and a collector, and wherein carriers are transported under the influence of biasing voltages, the improvement comprising the combination of at least one voltage biased compositional barrier located in the base adjacent the emitter and at least one voltage biased electrostatic barrier located in the base and interposed between the compositional barrier and the collector.

Claim 6

The structure of claim 3 wherein said compositional barrier is AlGaAs and said electrostatic barrier is p conductivity type.

Claim 7

The structure of claim 4 wherein said AlGaAs barrier has a first barrier energy level and said p type has a second barrier energy level higher than that of the AlGaAs barrier.

Claim 8

A compound semiconductor device of the type having multiple valley regions and where the carriers can be in one or other mass states, the semiconductor device further having an emitter element, a base element and a collector element, one side of the base element being contiguous with the collector element, the other side of said base element being contiguous with said emitter element for forming a heterojunction, the improvement comprising: said emitter element having a high carrier density portion adjacent an external electrode and having a second portion for forming a specific barrier height located adjacent said heterojunction with said base element, said second portion having a first band gap; said base element having a second band gap smaller than said first band gap of said emitter element; having means for confining low energy carriers from the emitter element in a potential well adjacent said heterojunction, having means adjacent said collector element operable to confine ballistic carriers to low effective mass to prevent the ballistic carriers from transferring to a high effective mass satellite conduction band valley of the semiconductor, and having an external electrode; said collector element having a high conductivity portion, and having an external electrode.

Claim 9

A compound semiconductor device of the type having multiple valley regions and where the carriers can be in one or other mass states, the semiconductor device further having an emitter element, a base element and a collector element, one side of the base element being contiguous with the collector element, the other side of said base element being contiguous with said emitter element for forming a heterojunction, the improvement comprising: said emitter element having a high carrier density portion adjacent an external electrode and having a second portion for forming a specific barrier height located adjacent said heterojunction with said base element, said second portion having a first band gap; said base element having a second band gap smaller than said first band gap of said emitter element; having means for confining low energy carriers from the emitter element in a potential well adjacent said heterojunction, having means adjacent said collector element operable to confine ballistic carriers to low effective mass to prevent the ballistic carriers from transferring to a high effective mass satellite conduction band valley of the semiconductor, and having an external electrode; said collector element having a high conductivity portion, and having an external electrode.

Claim 10

The device of claim 6 wherein said carrier confining means and said low effective mass confining means are respective voltage biased barriers.

Claim 11

The device of claim 7 wherein said carrier confining barrier is effected by a localizing change in band gap due to a change in semiconductor composition and said low effective mass confinement means is a planar doped barrier.

Claim 12

The device of claim 8 wherein said semiconductor is GaAs and said composition change is produced by the addition of Al.

Claim 13

The device of claim 7 wherein said carrier confinement barrier is a planar doped barrier and said low effective mass confinement means is a planar doped barrier.

Claim 14

The device of claim 10 where said semiconductor is GaAs.

Claim 15

The device of claim 9 wherein said emitter element is n type and graded from GaAs adjacent said external electrode to intrinsic AlGaAs, said heterojunction being adjacent to said intrinsic AlGaAs, and wherein said base element is undoped GaAs adjacent said second junction.

Claim 16

The device of claim 12 wherein said carrier confining means is a region of AlGaAs.

Claim 17

The device of claim 13 wherein said AlGaAs portion of said emitter element is Al 0 .3 Ga 0 .7 As and said carrier confining means is Al 0 .1 Ga 0 .9 As.

Claim 18

A semiconductor device having a collector portion, a base portion, and an emitter portion, a potential well formed in the base portion adjacent the emitter portions, the device comprising: a degenerative two-dimensional carrier gas layer in the potential well; a layer between said gas layer and said collector portion for providing a low energy barrier to confine low energy electrons traveling from said emitter portion to said collector portion in said potential well under a bias voltage; and a planar doped type barrier between said low energy barrier layer and said collector portion for permitting ballistic carriers to transport from said emitter portion to said collector portion, but preventing the same from acquiring enough energy for intervalley scattering.

Claim 19

A semiconductor device having a collector portion, a base portion, and an emitter portion, a potential well formed in the base portion adjacent the emitter portions, the device comprising: a degenerative two-dimensional carrier gas layer in the potential well; a layer between said gas layer and said collector portion for providing a low energy barrier to confine low energy electrons traveling from said emitter portion to said collector portion in said potential well under a bias voltage; and a planar doped type barrier between said low energy barrier layer and said collector portion for permitting ballistic carriers to transport from said emitter portion to said collector portion, but preventing the same from acquiring enough energy for intervalley scattering.

Claim 20

The semiconductor device of claim 15 wherein said second layer is intrinsic AlGaAs.

Claim 21

In a semiconductor three-terminal structure of the type where carriers in a semiconductor crystal material are launched from an emitter for transport across a base to collector, each of said emitter, base, and collector having electrode means connected thereto, said semiconductor structure comprising: a potential well adjacent said emitter; a low energy barrier between said potential well and said collector confining low energy carriers transversing from said emitter to said collector in said potential well under a bias voltage; and a planar doped type barrier interposed between said low energy barrier and said collector for permitting ballistic carriers to traverse from said emitter to said collector without said carriers losing substantial energy and velocity.

Claim 22

In a semiconductor three-terminal structure of the type where carriers in a semiconductor crystal material are launched from an emitter for transport across a base to collector, each of said emitter, base, and collector having electrode means connected thereto, said semiconductor structure comprising: a potential well adjacent said emitter; a low energy barrier between said potential well and said collector confining low energy carriers transversing from said emitter to said collector in said potential well under a bias voltage; and a planar doped type barrier interposed between said low energy barrier and said collector for permitting ballistic carriers to traverse from said emitter to said collector without said carriers losing substantial energy and velocity.

Claim 23

The semiconductor structure of claim 17 wherein said low energy barrier is a compositional barrier and wherein said planar doped type barrier is an electrostatic barrier.