US5040042A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bidirectional semiconductor component that can be turned off
Assignee: ABB Asea Brown Boveri Ltd
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Filing: 1990-04-25
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Granted: 1991-08-13
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Expires: 2010-04-25
Abstract
Abstract In the case of a symmetrically constructed TRIAC, which comprises a semiconductor substrate (20) with an internal n-base layer (9), two adjoining p-base layers (7, 11), two n-emitter regions (4, 12) let into the p-base layers (7, 11), two main electrodes (1, 17) arranged on the principal faces (29, 30), and two firing devices, a simplified control is achieved by means of MOS-controlled short circuits (3, 5, 6, 7 or 11, 13, 14, 16) at the n-emitter regions (4 or 12).
Inventors
- 👤 Friedhelm Bauer
- 👤 Thomas Stockmeier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:50
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/60; H10D18/65; H10D18/655; H10D18/80
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
513 words
A bidirectional semiconductor component that can be turned off, comprising: a semiconductor substrate bounded by first and second principal faces and divided laterally into a plurality of adjacent first and second regions, said semiconductor substrate including in its interior a first base layer of a first conductivity type which extends continuously through said first and second regions; a first main electrode deposited on said first principal face and connected to a first main terminal; a second main electrode deposited on said second principal face and connected to a second main terminal; within each of said first regions a second base layer of a second conductivity type which is opposite to said first conductivity type, said second base layer projecting from said first principal face into said first base layer of said semiconductor substrate; within each of said second regions a third base layer of said second conductivity type, said third base layer projecting from said second principal face into said first base layer of said semiconductor substrate; within each of said first regions a first emitter region of said first conductivity type projecting from said first principal face into said second base layer and contacting said first main electrode; within each of said second regions a second emitter region of said first conductivity type projecting from said second principal face into said third base layer and contacting said second main electrode; within each of said first regions a third emitter region of said second conductivity type projecting towards said first principal face from said second principal face into said first base layer and being contacted by said second main electrode; within each of said second regions a fourth emitter region of said second conductivity type projecting towards said second principal face from said first principal face into said first base layer and being contacted by said first main electrode; along the periphery of each of said first emitter regions a first, MOS-controlled short for short circuiting said first emitter region, said first short comprising, a first source region of said second conductivity type which projects from said first principal face into said semiconductor substrate and is connected to said first main electrode, said second base layer, a first channel region of said first conductivity type which is arranged between said first source region and said second base layer, and a first gate electrode which is arranged above said first channel region and is isolated from said semiconductor substrate; along the periphery of each of said second emitter regions a second, MOS-controlled short for short circuiting said second emitter region, said second short comprising, a second source region of said second conductivity type which projects from second principal face into said semiconductor substrate and is connected to said second main electrode, said third base layer, a second channel region of said first conductivity type which is arranged between said second source region and said third base layer, and a second gate electrode which is arranged above said second channel region and is isolated from said semiconductor substrate; and means for activating said semiconductor component.
Claim 2
Dependent Claim
513 words
A bidirectional semiconductor component that can be turned off, comprising: a semiconductor substrate bounded by first and second principal faces and divided laterally into a plurality of adjacent first and second regions, said semiconductor substrate including in its interior a first base layer of a first conductivity type which extends continuously through said first and second regions; a first main electrode deposited on said first principal face and connected to a first main terminal; a second main electrode deposited on said second principal face and connected to a second main terminal; within each of said first regions a second base layer of a second conductivity type which is opposite to said first conductivity type, said second base layer projecting from said first principal face into said first base layer of said semiconductor substrate; within each of said second regions a third base layer of said second conductivity type, said third base layer projecting from said second principal face into said first base layer of said semiconductor substrate; within each of said first regions a first emitter region of said first conductivity type projecting from said first principal face into said second base layer and contacting said first main electrode; within each of said second regions a second emitter region of said first conductivity type projecting from said second principal face into said third base layer and contacting said second main electrode; within each of said first regions a third emitter region of said second conductivity type projecting towards said first principal face from said second principal face into said first base layer and being contacted by said second main electrode; within each of said second regions a fourth emitter region of said second conductivity type projecting towards said second principal face from said first principal face into said first base layer and being contacted by said first main electrode; along the periphery of each of said first emitter regions a first, MOS-controlled short for short circuiting said first emitter region, said first short comprising, a first source region of said second conductivity type which projects from said first principal face into said semiconductor substrate and is connected to said first main electrode, said second base layer, a first channel region of said first conductivity type which is arranged between said first source region and said second base layer, and a first gate electrode which is arranged above said first channel region and is isolated from said semiconductor substrate; along the periphery of each of said second emitter regions a second, MOS-controlled short for short circuiting said second emitter region, said second short comprising, a second source region of said second conductivity type which projects from second principal face into said semiconductor substrate and is connected to said second main electrode, said third base layer, a second channel region of said first conductivity type which is arranged between said second source region and said third base layer, and a second gate electrode which is arranged above said second channel region and is isolated from said semiconductor substrate; and means for activating said semiconductor component.
Claim 3
Dependent Claim
75 words
The semiconductor component as claimed in claim 1, wherein said activating means comprises: a first gate metallic coating provided on said first principal face beside said first main electrode and connected to a first firing activating gate contact, and contacting said second base layer; and a second gate metallic coating provided on said second principal face beside said second main electrode and connected to a second activating gate contact, and contacting said third base layer.
Claim 4
Dependent Claim
196 words
The semiconductor component as claimed in claim 1, wherein said activating means comprise: along the periphery of each of said third emitter regions a third, MOS-controlled short for short circuiting said third emitter region, said third short comprising: a third source region of said first conductivity type which projects from said second principal face into said semiconductor substrate and is connected to said second main electrode, said first base layer, a third channel region of said second conductivity type which is arranged between said third source region and said first base layer, and said second gate electrode which extends above said third channel region; and along the periphery of each of said fourth emitter regions a fourth, MOS-controlled short for short circuiting said fourth emitter region, said fourth short comprising: a fourth source region of said first conductivity type which projects from said first principal face into said semiconductor substrate and is connected to said first main electrode, said first base layer, a fourth channel region of said second conductivity type which is arranged between said fourth source region and said first base layer, and said first gate electrode which extends above said fourth channel region.
Claim 5
Dependent Claim
31 words
The semiconductor component as claimed in one of the claims 1 to 3, wherein said first conductivity type is of the n-type and said second conductivity type is of the p-type.
Claim 6
Dependent Claim
61 words
The semiconductor component as claimed in claim 4, wherein said first base layer is n - -doped, said second and third base layers are p-doped, said first and second emitter regions are n + -doped, said third and fourth emitter regions and said first and second source regions are p + -doped and said first and second channel regions are n-doped.
Claim 7
Dependent Claim
26 words
The semiconductor component as claimed in one of the claims 1 to 3, wherein said first and second gate electrodes project vertically into said semiconductor substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-12 | 1995-02-11 | 1995-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-12 | 1999-02-11 | 1999-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-12 | 2003-02-11 | 2003-08-13 | $7700.00 | Window Closed / Lapsed |