Abstract A fault tolerant register employing triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The fault tolerant register includes a single master multiplexer, three slave multiplexers connected in parallel to the output of the master multiplexer and three voting circuits positioned in feedback paths of the slave multiplexers. The slave multiplexers provide triple redundant storage for the data and the voting circuits correct any data that might become disrupted. The fault tolerant register of the present invention provides greatly improved SEU tolerance without a large increase in circuit area or without resorting to error correction and its attendant scrubbing process.
A fault tolerant register, comprising: a master multiplexer; three or more slave multiplexers connected in parallel to the output of the master multiplexer, each slave multiplexer having a feedback path; and a voting circuit positioned in the feedback path of each slave multiplexer, the outputs of the slave multiplexers being applied to all of the voting circuits; wherein the outputs of the voting circuits correspond to the outputs of a majority of the slave multiplexers, thereby correcting any incorrect data stored in one or more of the slave multiplexers.
Claim 2
Dependent Claim
89 words
A fault tolerant register, comprising: a master multiplexer; three or more slave multiplexers connected in parallel to the output of the master multiplexer, each slave multiplexer having a feedback path; and a voting circuit positioned in the feedback path of each slave multiplexer, the outputs of the slave multiplexers being applied to all of the voting circuits; wherein the outputs of the voting circuits correspond to the outputs of a majority of the slave multiplexers, thereby correcting any incorrect data stored in one or more of the slave multiplexers.
Claim 3
Dependent Claim
44 words
The fault tolerant register as recited in claim 1, and further including: an out-of-phase clock signal for driving the master multiplexer; and an in-phase clock signal for driving the slave multiplexers; wherein the slave multiplexers store data when the in-phase clock signal is low.
Claim 4
Dependent Claim
17 words
The fault tolerant register as recited in claim 1, wherein the master multiplexer includes a feedback path.