US4617475A
Expired / Lapsed
US
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Wired logic voting circuit
Assignee: Intel Corp
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Filing: 1984-03-30
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Granted: 1986-10-14
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Expires: 2004-03-30
Abstract
Abstract A wired voting circuit is described providing an output which follows the majority of input logic levels according to the equation: F=AB+AC+BC. A non-inverting signal voting node (D) and an inverting signal voting node (E) comprise a first and a second collector of an odd number of input differential transistor pairs (30, 32, 34) wherein said nodes are formed by wiring all of said first collectors together at one signal node and by wiring all of said second collectors together at the other signal node. Each signal node is coupled to a differential input of an output differential transistor pair (36). Currents are steered by the state of input logic onto either of the signal nodes, depending upon the input logic signal level. The signal level at each voting node is proportional to the number of input differential transistor pairs that steer current to the voting node. The voting scheme employs an odd number of logic inputs (T, U, V), such that an odd number of currents (I x , I y , I z ) are steered to the voting nodes. Therefore, the signal level at a first voting node is never equal to that of the other voting node during a steady state condition; the signal level difference between the two voting nodes is indicative of the majority state of the input logic signals. An output differential transistor pair compares the signal level difference and translates it to voltage levels compatible with other signals in the system in which the invention is used. By providing redundant signal pathways, signal processing reliability is enhanced. Monolithic device yields are improved by providing for diagnosis of faulty signal pathways and elimination thereof.
Inventors
- 👤 Robert M. Reinschmidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:57
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/23; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0866
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
355 words
A wired logic voting circuit providing an output which follows the majority of input logic levels according to the formula: F=AB+AC+BC where F is the output of the function described and A, B, and C are the voting input signals, comprising: a plurality of differential input logic elements, each of said elements comprising a differential transistor pair, the base of a first transistor of said transistor pair providing a voting input, the base of the second transistor of said transistor pair coupled to a reference level signal, the emitters of said transistor pair coupled together at a current sink, the collector of the first transistor of said transistor pair coupled through a resistor to a voltage source to provide a first logic level signal, the collector of the second transistor of said transistor pair coupled through a resistor to said voltage source to provide a second, opposite logic level signal, the collectors of the first transistors for all of said differential transistor pairs being wired together at a first signal node, the collectors of the second transistors for all of said differential transistor pairs being wired together at a second signal node; an output differential transistor pair, including a first transistor having a base coupled to said first signal node and including a second transistor having a base coupled to said second signal node, the emitters of said output differential transistor pair being coupled together at a current sink, the collector of said first transistor of said output differential transistor pair being coupled through a resistor to a voltage source to provide an actuating output logic level signal, the collector of said second transistor of said output differential transistor pair being coupled to said voltage source, wherein a signal level at one signal node is never equal to a signal level at the other signal node and wherein the polarity of signal level difference between the two signal nodes indicates the majority state of the input logic signals; and a diagnositic circuit, coupled between the emitters of said logic element transistor pair and said current sink, for locating and isolating defective logic element transistor pairs.
Claim 2
Dependent Claim
355 words
A wired logic voting circuit providing an output which follows the majority of input logic levels according to the formula: F=AB+AC+BC where F is the output of the function described and A, B, and C are the voting input signals, comprising: a plurality of differential input logic elements, each of said elements comprising a differential transistor pair, the base of a first transistor of said transistor pair providing a voting input, the base of the second transistor of said transistor pair coupled to a reference level signal, the emitters of said transistor pair coupled together at a current sink, the collector of the first transistor of said transistor pair coupled through a resistor to a voltage source to provide a first logic level signal, the collector of the second transistor of said transistor pair coupled through a resistor to said voltage source to provide a second, opposite logic level signal, the collectors of the first transistors for all of said differential transistor pairs being wired together at a first signal node, the collectors of the second transistors for all of said differential transistor pairs being wired together at a second signal node; an output differential transistor pair, including a first transistor having a base coupled to said first signal node and including a second transistor having a base coupled to said second signal node, the emitters of said output differential transistor pair being coupled together at a current sink, the collector of said first transistor of said output differential transistor pair being coupled through a resistor to a voltage source to provide an actuating output logic level signal, the collector of said second transistor of said output differential transistor pair being coupled to said voltage source, wherein a signal level at one signal node is never equal to a signal level at the other signal node and wherein the polarity of signal level difference between the two signal nodes indicates the majority state of the input logic signals; and a diagnositic circuit, coupled between the emitters of said logic element transistor pair and said current sink, for locating and isolating defective logic element transistor pairs.
Claim 3
Dependent Claim
110 words
The voting circuit of claim 1, further comprising: a plurality of differential diagnostic elements coupled in parallel with said differential input logic elements and being operable to receive a diagnostic data signal; means for selecting between operation of said differential input logic elements and said differential diagnostic elements in response to a diagnostic select signal; means for selectively disabling the operation of at least one of said differential input logic elements in response to a logic element disable signal provided during a diagnostic sequence initiated by said diagnostic data signal; and means, responsive to a programming signal, for isolating defective differential input logic elements from said wired logic voting circuit.
Claim 4
Dependent Claim
14 words
The voting circuit of claim 2, said means for isolating comprising a cutable link.
Claim 5
Dependent Claim
493 words
A redundant wired logic voting circuit providing an output which follows the majority of input logic levels according to the formula: F=AB+AC+BC where F is the output of the function described and A, B, and C are the voting input signals, comprising: a first plurality of differential input logic elements, each of said elements comprising a differential transistor pair, the base of a first transistor of said transistor pair providing a first voting input, the base of the second transistor of said transistor pair coupled to a reference level signal, the emitters of said transistor pair coupled together at a current sink, the collector of the first transistor of said transistor pair coupled through a resistor to a voltage source to provide a first logic level signal, the collector of the second transistor of said transistor pair coupled through a resistor to said voltage source to provide a second, opposite logic level signal, the collectors of the first transistors for all of said differential transistor pairs being wired together at a first signal node, the collectors of the second transistors for all of said differential transistor pairs being wired together at a second signal node; a second plurality of differential input logic elements, each of said elements comprising a differential transistor pair, the base of a first transistor of said transistor pair coupled to said first node, the base of the second transistor of said transistor pair coupled to said second node, the emitters of said transistor pair coupled together at a current sink, the collector of the first transistor of said transistor pair coupled through a resistor to a voltage source to provide a first output logic level signal, the collector of the second transistor of said transistor pair coupled through a resistor to said voltage source to provide a second, opposite output logic level signal, the collectors of the first transistors for all of said differential transistor pairs being wired together at a first output signal node, the collectors of the second transistors for all of said differential transistor pairs being wired together at a second output signal node; and an output differential transistor pair, including a first transistor having a base coupled to said first output signal node and including a second transistor having a base coupled to said second output signal node, the emitters of said output differential transistor pair being coupled together at a current sink, the collector of said first transistor of said output differential transistor pair being coupled through a resistor to a voltage source to provide an actuating output logic level signal, the collector of said second transistor of said output differential transistor pair being coupled to said voltage source, wherein a signal level at one output signal node is never equal to a signal level at the other output signal node and wherein the polarity of signal level difference between the two output signal nodes indicates the majority state of the input logic signals.
Claim 6
Dependent Claim
493 words
A redundant wired logic voting circuit providing an output which follows the majority of input logic levels according to the formula: F=AB+AC+BC where F is the output of the function described and A, B, and C are the voting input signals, comprising: a first plurality of differential input logic elements, each of said elements comprising a differential transistor pair, the base of a first transistor of said transistor pair providing a first voting input, the base of the second transistor of said transistor pair coupled to a reference level signal, the emitters of said transistor pair coupled together at a current sink, the collector of the first transistor of said transistor pair coupled through a resistor to a voltage source to provide a first logic level signal, the collector of the second transistor of said transistor pair coupled through a resistor to said voltage source to provide a second, opposite logic level signal, the collectors of the first transistors for all of said differential transistor pairs being wired together at a first signal node, the collectors of the second transistors for all of said differential transistor pairs being wired together at a second signal node; a second plurality of differential input logic elements, each of said elements comprising a differential transistor pair, the base of a first transistor of said transistor pair coupled to said first node, the base of the second transistor of said transistor pair coupled to said second node, the emitters of said transistor pair coupled together at a current sink, the collector of the first transistor of said transistor pair coupled through a resistor to a voltage source to provide a first output logic level signal, the collector of the second transistor of said transistor pair coupled through a resistor to said voltage source to provide a second, opposite output logic level signal, the collectors of the first transistors for all of said differential transistor pairs being wired together at a first output signal node, the collectors of the second transistors for all of said differential transistor pairs being wired together at a second output signal node; and an output differential transistor pair, including a first transistor having a base coupled to said first output signal node and including a second transistor having a base coupled to said second output signal node, the emitters of said output differential transistor pair being coupled together at a current sink, the collector of said first transistor of said output differential transistor pair being coupled through a resistor to a voltage source to provide an actuating output logic level signal, the collector of said second transistor of said output differential transistor pair being coupled to said voltage source, wherein a signal level at one output signal node is never equal to a signal level at the other output signal node and wherein the polarity of signal level difference between the two output signal nodes indicates the majority state of the input logic signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-13 | 1990-04-14 | 1990-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-13 | 1994-04-14 | 1994-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-13 | 1998-04-14 | 1998-10-14 | $7700.00 | Window Closed / Lapsed |