System for expanded detection and correction of errors in parallel binary data produced by data tracks

Claim 2

Apparatus for detecting errors in a parallel binary data pattern made of a plurality of binary bits, each of said bits being respectively produced by one of a plurality of data tracks comprising means for receiving the bits produced by said tracks and detecting which tracks are in an inalterable condition; means receiving the parallel data pattern for detecting the presence of bit error condition in said binary data and for indicating the proper bit position in said data pattern of an error only when a single error is present in said pattern; means responsive to said two previous means for determining if said indicated bit error is coincident with a track determined to be in an inalterable condition.

Claim 3

The apparatus of claim 1 wherein each of the tracks comprises cycling sequential binary data bits containing at least one check bit which is the binary complement of the next preceding bit, and said means for detecting which tracks are in an inalterable condition comprise: means for detecting a change in the binary state in each of said cycling data tracks means for cycling said tracks so that each of said check bits and next preceding bits pass said detecting means, and means responsive to each of said detecting means for indicating that the track corresponding to the detecting means is in an inalterable condition in the absence of a detected change.

Claim 4

The apparatus of claim 1 wherein said error detecting and indicating means are Hamming Error detecting means.

Claim 5

The apparatus of claim 1, further including means associated with said inalterable track detecting means for counting the inalterable tracks, means receiving the parallel data pattern for detecting the presence of a parity error in the binary data pattern, means responsive to said parity error-detecting means, bit error-detecting means, coincidence determining means, said inalterable track detecting means and said inalterable track counting means for correlating said detected parity error, bit error, coincident and inalterable track conditions with said inalterable track count, and complementing means responsive to said correlating means for selectively complementing bits produced by at least one of said inalterable tracks when said correlated conditions and count correspond to a predetermined combination of said conditions and count.

Claim 6

The apparatus of claim 4 wherein each of the tracks comprises cycling sequential binary data bits containing at least one check bit which is the binary complement of the next preceding bit, and said means for detecting which tracks are in an inalterable condition comprise: means for detecting a change in the binary state in each of said cycling data tracks means for cycling said tracks so that each of said check bits and next preceding bits pass said detecting means, and means responsive to each of said detecting means for indicating that the track corresponding to the detecting means is in an inalterable condition in the absence of a detected change.

Claim 7

The apparatus of claim 1, further including means associated with said inalterable track detecting means for counting the inalterable tracks, means receiving the parallel datA pattern for detecting the presence of a parity error in the binary data pattern, means responsive to said parity error-detecting means, bit error-detecting means, coincidence determining means, said inalterable track detecting means and said inalterable track counting means for correlating said detected parity error, bit error, coincident error and inalterable track conditions with said inalterable track count, and correcting means responsive to said correlating means for selectively correcting said indicated bit position error when said correlated conditions and count correspond to a predetermined combination of said conditions and count.

Claim 8

The apparatus of claim 6 wherein said bit error detecting and indicating means are Hamming Error detecting means and said means for correcting said indicated bit position error are Hamming Error correction means.

Claim 9

The apparatus of claim 6 further including complementing means responsive to said correlating means for selectively complementing bits produced by at least one of said inalterable tracks when said correlated conditions and count correspond to a predetermined combination of said conditions and count.

Claim 10

The apparatus of claim 6 wherein said correcting means respond to a predetermined combination with a count of two.

Claim 11

The apparatus of claim 8 wherein said correcting means respond to a predetermined combination with a count of two.

Claim 12

The apparatus of claim 5 wherein said complementing means respond to a predetermined combination in which there is a bit error condition and no parity error.

Claim 13

The apparatus of claim 8 wherein said complementing means respond to a predetermined combination in which there is a bit error condition and no parity error.

Claim 14

The apparatus of claim 4 wherein said complementing means respond to a predetermined combination in which there is a bit error condition, no parity error, two inalterable tracks and a coincident condition, and said complementing means complement only the inalterable track which is not coincident with said indicated random error bit position.

Claim 15

The apparatus of claim 13 wherein said error detecting and indicating means are Hamming Error detecting means.

Claim 16

The apparatus of claim 8, further including means responsive to said inalterable track counting means for halting the apparatus when the count of inalterable tracks is at least three.

Claim 17

The apparatus of claim 1 wherein each of said tracks is a shift register.

Claim 18

The apparatus of claim 8 wherein each of said tracks is a shift register.

Claim 19

The apparatus of claim 16 wherein said shift registers are integrated semiconductor circuits.

Claim 20

The apparatus of claim 17 wherein said shift registers are integrated semiconductor circuits.

Claim 21

Apparatus for detecting and correcting errors in a parallel binary data pattern made of a plurality of binary bits, each of said bits being respectively produced by one of a plurality of data tracks comprising means for receiving the bits produced by said tracks and determining which tracks are in an inalterable condition; means associated with said inalterable track determining means for counting the number of tracks in said inalterable condition; means responsive to said inalterable track counting means for halting the apparatus when the count of inalterable tracks is at least three; first detecting means receiving the parallel data pattern for detecting the presence of a parity error in the parallel binary data pattern; second detecting means receiving the parallel data pattern for detecting the presence of a bit error condition in said binary data and for indicating one of the bits in said data pattern, said indicated bit being in error only when there is a single error in said binary data pattern; means for applying said binary data pattern to said first and second detecting means; means, responsive to said first and second detecting means and said inalterable tracK determining means and activated by the combination of the absence of a parity error and the presence of a bit error condition in the applied data pattern, for complementing the bits in said parallel data pattern produced by tracks in inalterable condition; means for reapplying said complemented data pattern produced by said complementing means to said first and second detecting means; means responsive to said first and second detecting means for providing an error output signal if said reapplied complemented data pattern still results in the combinations of the absence of a parity error and the presence of an error condition; means responsive to said first and second detecting means for passing the original or reapplied data pattern as a good pattern in the absence of both said parity error and error condition; means, responsive to said first and second detecting means and said inalterable track counting means and activated by the combination of the presence of a parity error and an indicated bit error in the original or reapplied data pattern and an inalterable track count of less than two, for correcting said indicated bit error and for passing the corrected data pattern as a good pattern; means, responsive to said inalterable track determining means and said bit error detecting means, for determining if said indicated bit error is coincident with a stuck track; and means, responsive to said first and second detecting means, said inalterable track counting means, coincidence determining means and said inalterable track determining means and activated by the combination of the presence of a parity error and an indicated bit error in the original or reapplied data pattern and an inalterable track count of two for correcting said indicated bit error and for passing the corrected data pattern if said indicated bit error is coincident with a stuck track, or for providing an error output signal if said indicated bit error is not coincident with a stuck track.

Claim 22

Apparatus for detecting and correcting errors in a parallel binary data pattern made of a plurality of binary bits, each of said bits being respectively produced by one of a plurality of data tracks comprising means for receiving the bits produced by said tracks and determining which tracks are in an inalterable condition; means associated with said inalterable track determining means for counting the number of tracks in said inalterable condition; means responsive to said inalterable track counting means for halting the apparatus when the count of inalterable tracks is at least three; first detecting means receiving the parallel data pattern for detecting the presence of a parity error in the parallel binary data pattern; second detecting means receiving the parallel data pattern for detecting the presence of a bit error condition in said binary data and for indicating one of the bits in said data pattern, said indicated bit being in error only when there is a single error in said binary data pattern; means for applying said binary data pattern to said first and second detecting means; means, responsive to said first and second detecting means and said inalterable tracK determining means and activated by the combination of the absence of a parity error and the presence of a bit error condition in the applied data pattern, for complementing the bits in said parallel data pattern produced by tracks in inalterable condition; means for reapplying said complemented data pattern produced by said complementing means to said first and second detecting means; means responsive to said first and second detecting means for providing an error output signal if said reapplied complemented data pattern still results in the combinations of the absence of a parity error and the presence of an error condition; means responsive to said first and second detecting means for passing the original or reapplied data pattern as a good pattern in the absence of both said parity error and error condition; means, responsive to said first and second detecting means and said inalterable track counting means and activated by the combination of the presence of a parity error and an indicated bit error in the original or reapplied data pattern and an inalterable track count of less than two, for correcting said indicated bit error and for passing the corrected data pattern as a good pattern; means, responsive to said inalterable track determining means and said bit error detecting means, for determining if said indicated bit error is coincident with a stuck track; and means, responsive to said first and second detecting means, said inalterable track counting means, coincidence determining means and said inalterable track determining means and activated by the combination of the presence of a parity error and an indicated bit error in the original or reapplied data pattern and an inalterable track count of two for correcting said indicated bit error and for passing the corrected data pattern if said indicated bit error is coincident with a stuck track, or for providing an error output signal if said indicated bit error is not coincident with a stuck track.

Claim 23

The apparatus of claim 20 wherein each of said data tracks is a shift register.

Claim 24

The apparatus of claim 20, wherein said second detecting means are Hamming Error detection means and said means for correcting the indicated bit error are Hamming Error correction means.

Claim 25

The apparatus of claim 21 wherein said shift register is an integrated semiconductor circuit.

Claim 26

The apparatus of claim 20 wherein at least one of said means for providing an error output signal also halts the apparatus upon providing said error signal.

Claim 27

Apparatus for detecting whether a track of cycling sequential binary data bits is in an inalterable condition comprising means for complementing one of said bits in said track and for inserting said complemented bit into said track as a check bit, means for detecting a change in the binary state in said cycling data track, means for cycling said track so that said check bit and its corresponding original bit pass said detecting means, and means responsive to said detecting means for indicating that the track is in an inalterable condition in the absence of said detected change.

Claim 28

Apparatus for detecting whether a track of cycling sequential binary data bits is in an inalterable condition comprising means for complementing one of said bits in said track and for inserting said complemented bit into said track as a check bit, means for detecting a change in the binary state in said cycling data track, means for cycling said track so that said check bit and its corresponding original bit pass said detecting means, and means responsive to said detecting means for indicating that the track is in an inalterable condition in the absence of said detected change.

Claim 29

The apparatus of claim 25, wherein the entire data track is cycled past said detecting means, thereby insuring that the check bit and the original bit will be cycled past said detecting means.

Claim 30

The apparatus of claim 25 wherein said detecting and indicating means comprise a bistable circuit to which said check bit and said original bit are sequentially applied, the output state of said bistable circuit indicating whether there has been a change in binary state between said two applied bits.

Claim 31

The apparatus of claim 25 wherein said original bit passes said detection means immediately preceding said check bit.

Claim 32

Apparatus for detecting whether any of a plurality of tracks of cycling sequential binary data bits are in an inalterable condition comprising means for complementing one of saiD bits in each of said plurality of tracks and for inserting each of said complemented bits respectively into said plurality of tracks as check bits, means for detecting a change in the binary state in each of said cycling data tracks, means for cycling said tracks so that each of said check bits and their original bits pass said detecting means, and means responsive to each of said detecting means for indicating that the track corresponding to the detecting means is in an inalterable condition in the absence of a detected change.

Claim 33

Apparatus for detecting whether any of a plurality of tracks of cycling sequential binary data bits are in an inalterable condition comprising means for complementing one of saiD bits in each of said plurality of tracks and for inserting each of said complemented bits respectively into said plurality of tracks as check bits, means for detecting a change in the binary state in each of said cycling data tracks, means for cycling said tracks so that each of said check bits and their original bits pass said detecting means, and means responsive to each of said detecting means for indicating that the track corresponding to the detecting means is in an inalterable condition in the absence of a detected change.

Claim 34

The apparatus of claim 29 wherein each of said original bits passes its respective detection means immediately preceding its respective check bit in each of said tracks.

Claim 37

The method of claim 31, further including the steps of counting the inalterable tracks, detecting the presence of a parity error in the binary data pattern, correlating said detected parity error, bit error, coincident and inalterable track conditions with said inalterable track count, and selectively complementing bits produced by at least one of said inalterable tracks when said correlated conditions and count correspond to a predetermined combination of said conditions and count.

Claim 38

The method of claim 31, further including the steps of counting the inalterable tracks, detecting the presence of a parity error in the binary data pattern, correlating said detected parity error, bit error, coincident error and inalterable track conditions with said inalterable track count, and selectively correcting said indicated Hamming error when said correlated conditions and count correspond to a predetermined combination of said conditions and count.

Claim 39

The method of claim 33, further including the step of selectively complementing bits produced by at least one of said inalterable tracks when said correlated conditions and count correspond to a predetermined combination of said conditions and count.

Claim 40

The method of claim 34 wherein said selective correction is made when said predetermined combination includes a count of two.

Claim 41

The method of claim 32 wherein said selective complementing is made when said predetermined combination includes a bit error condition, no parity error, two inalterable tracks and a coincident condition, and only the inalterable track which is not coincident with said indicated random error bit position is complemented.