Scannable asynchronous/synchronous CMOS latch

Claim 2

A scannable latch circuit comprising: first latch means, operable in a first mode of operation, for providing and maintaining a first data bit output signal at a first level in response to a specified change in a data bit input signal applied to an input terminal of said scannable latch circuit, said first data bit output signal being connected to a first output terminal; reset means, also operable in said first mode of operation, for resetting said first data bit output signal to a second level in response to a reset signal applied to a reset terminal of said scannable latch circuit; second latch means, operable in a second mode of operation for providing and maintaining a second data bit output signal connected to a second output terminal, and having a level that is equivalent to the level of said data bit input signal immediately prior to the occurrence of a specified transition in a first clock signal applied to a clock terminal of said scannable latch circuit, said second latch means maintaining the level of the second data bit output signal for the entire duration of a cycle of said first clock signal; shift means, operable in a third mode of operation, for selectively allowing data bit signals to be shifted into or out of said second latch means, said shift means including output means for shifting said data bit signals out of second latch means that is separate from said first and second data bit output signals provided by said first and second modes of operation, respectively; and select means for selecting the mode of operation of said scannable latch circuit, and for controlling the operation thereof.

Claim 3

The scannable latch of claim 1 wherein said first latch means comprises an asynchronous latch circuit comprising; an AND gate having a plurality of inputs and one output, one of said inputs being coupled to the reset terminal of said scannable latch circuit; a NOR gate having at least two inputs, one of its inputs being coupled to the output of the AND gate and the other of its inputs being coupled to the input terminal of said scannable latch circuit and having an output connected to said first output terminal of said scannable latch circuit; and a first inverter gate having a single input and a single output, the input of the inverter gate being coupled to an output of the NOR gate, and the output of the inverter gate being coupled to one of the inputs of the AND gate.

Claim 4

The scannable latch circuit of claim 2 wherein said asynchronous latch circuit further includes a second inverter gate having an input connected to the output of the NOR gate, and an output connected to a third output terminal of said scannable latch circuit.

Claim 5

The scannable latch circuit of claim 2 wherein said first inverter gate comprises an element of said second latch means, the input of said first inverter gate being coupled to the output of the NOR gate through a plurality of logic elements of said second latch means, the output of said first inverter gate being further coupled to a second output terminal of said scannable latch circuit, said second data bit output signal being provided on said second output terminal.

Claim 6

The scannable latch circuit of claim 1 wherein said second latch means comprises a first latch circuit connected serially to a second latch circuit, said first and second latch circuits operating respectively as master and slave latch circuits during said second mode of operation.

Claim 7

The scannable latch circuit of claim 5 wherein said output means of said shift means comprises a third latch circuit coupled to said second latch circuit, said second and third latch circuits operating respectively as master and slave latch circuits during said third mode of operation.

Claim 8

The scannable latch circuit of claim 6 further including means for passing the first data bit output signal of said first latch means through said second latch means, whereby data held in said first latch means may be transferred to said second latch means and shifted thereoutof through the output means of said shift means during said third mode of operation.

Claim 9

The scannable latch circuit of claim 5 wherein said first latch circuit is responsive to a second clock signal and said second latch circuit is responsive to a third clock signal, said second and third clock signals being derived from said first clock signal by logic elements included within said select means.

Claim 10

The scannable latch circuit of claim 8 wherein said select means comprises: first logic means for dividing said first clock signal into said second and third clock signals; and second logic means responsive to an enable signal for blocking said second and third clock signals during said first mode of operation and for allowing said second and third clock signals to be respectively delivered to said first and second latch circuits during said second mode of operation.

Claim 11

A scannable synchronous/asynchronous CMOS latch circuit comprising: a first latch circuit for latching a first output signal to a first level in response to a prescribed change in a data input signal applied to a first input terminal thereof, said first output signal being connected to a first output terminal and for latching the first output signal to a second level in response to the application of a reset signal applied to a reset terminal thereof, said latching characterized by occurring without reference to any clocking signals; a second latch circuit connected to receive said data input signal from said first latch circuit and to latch a second output signal to a signal equivalent to the level of said data input signal immediately prior to the occurrence of a specified transition in a first clock signal applied to a clock terminal of said scannable synchronous/asynchronous CMOS latch circuit, and to maintain the latch level of said second output signal for the entire duration of cycle of said first clock signal said second output signal being connected to a second output terminal; scanning means for selectively shifting data held in said second latch circuit to a third output terminal; input means for selectively shifting data applied to a second input terminal of said scannable synchronous/asynchronous CMOS latch circuit directly into said second latch circuit; and select means, responsive to control signals including said first clock signal, for generating control and clock signals to selectively control the operation of said scannable synchronous/asynchronous CMOS latch circuit.

Claim 12

A scannable synchronous/asynchronous CMOS latch circuit comprising: a first latch circuit for latching a first output signal to a first level in response to a prescribed change in a data input signal applied to a first input terminal thereof, said first output signal being connected to a first output terminal and for latching the first output signal to a second level in response to the application of a reset signal applied to a reset terminal thereof, said latching characterized by occurring without reference to any clocking signals; a second latch circuit connected to receive said data input signal from said first latch circuit and to latch a second output signal to a signal equivalent to the level of said data input signal immediately prior to the occurrence of a specified transition in a first clock signal applied to a clock terminal of said scannable synchronous/asynchronous CMOS latch circuit, and to maintain the latch level of said second output signal for the entire duration of cycle of said first clock signal said second output signal being connected to a second output terminal; scanning means for selectively shifting data held in said second latch circuit to a third output terminal; input means for selectively shifting data applied to a second input terminal of said scannable synchronous/asynchronous CMOS latch circuit directly into said second latch circuit; and select means, responsive to control signals including said first clock signal, for generating control and clock signals to selectively control the operation of said scannable synchronous/asynchronous CMOS latch circuit.

Claim 13

A LSI CMOS circuit chip comprising a plurality of scannable CMOS latch circuits, each scannable CMOS latch circuit comprising: a first latch circuit for latching a first output signal to a first level in response to a prescribed change in a data input signal applied to a first input terminal thereof, said first output signal being connected to a first output terminal, and for latching the first output signal to a second level in response to the application of a reset signal applied to a reset terminal thereof, said latching characterized by occurring without reference to any clocking signals; a second latch circuit connected to receive said data input signal from said first latch circuit and to latch a second output signal to a signal equivalent to the level of said data input signal immediately prior to the occurrence of a specified transition in a first clock signal applied to a clock terminal of said scannable synchronous/asynchronous CMOS latch circuit, and to maintain the latched level of sad second output signal for the entire duration of a cycle of said first clock signal said second output signal being connected to a second output terminal; scanning means for selectively shifting data held in said second latch circuit to a third output terminal; input means for selectively shifting data applied to a second input terminal of said scannable synchronous/asynchronous CMOS latch circuit directly into said second latch circuit; and select means, responsive to control signals including said first clock signal, for generating control clock signals to selectively control the operation of said scannable synchronous/asynchronous CMOS latch circuit; means for interconnecting the select means of each of said scannable CMOS latch circuits so that all operate in a same mode of operation in response to a first prescribed control signal applied to a control terminal of said chip.

Claim 14

A LSI CMOS circuit chip comprising a plurality of scannable CMOS latch circuits, each scannable CMOS latch circuit comprising: a first latch circuit for latching a first output signal to a first level in response to a prescribed change in a data input signal applied to a first input terminal thereof, said first output signal being connected to a first output terminal, and for latching the first output signal to a second level in response to the application of a reset signal applied to a reset terminal thereof, said latching characterized by occurring without reference to any clocking signals; a second latch circuit connected to receive said data input signal from said first latch circuit and to latch a second output signal to a signal equivalent to the level of said data input signal immediately prior to the occurrence of a specified transition in a first clock signal applied to a clock terminal of said scannable synchronous/asynchronous CMOS latch circuit, and to maintain the latched level of sad second output signal for the entire duration of a cycle of said first clock signal said second output signal being connected to a second output terminal; scanning means for selectively shifting data held in said second latch circuit to a third output terminal; input means for selectively shifting data applied to a second input terminal of said scannable synchronous/asynchronous CMOS latch circuit directly into said second latch circuit; and select means, responsive to control signals including said first clock signal, for generating control clock signals to selectively control the operation of said scannable synchronous/asynchronous CMOS latch circuit; means for interconnecting the select means of each of said scannable CMOS latch circuits so that all operate in a same mode of operation in response to a first prescribed control signal applied to a control terminal of said chip.

Claim 15

The LSI CMOS circuit chip of claim 11 wherein the scannable CMOS latch circuits operate in one of at least two modes of operation in response to said first prescribed control signal, a first mode of operation wherein the first latch circuit is operable, and a second mode of operation wherein the second latch circuit is operable.

Claim 16

The LSI CMOS circuit chip of claim 12 wherein the scannable CMOS latch circuits further operate in a third mode of operation in response to a second control signal applied to an additional control terminal of said chip, said third mode of operation being adapted to enable the scanning and input means of said scannable CMOS latch circuits.