Error correction method and apparatus

Claim 2

Error correction circuitry comprising means to generate a redundant byte, y 7 -y 0 , for each original byte, x 7 -x 0 , by modulo 2 addition of adjacent pairs of bits of said original byte, means to store both said original and redundant bytes in memory, means to recall said original and redundant bytes from memory, said recalled original and redundant bytes being represented as x a7 -x a0 and y a7 -y a0 , respectively, means to apply said recalled original and redundant bytes to two arrays of modulo 2 adders to obtain two new bytes represented as x b7 -x b0 and x c7 -x c0 , wherein x bn =x a (n+1) ⊕y an , and x cn =x a (n-1) ⊕y a (n-1), and means to apply corresponding bits of said new bytes and said recalled original byte to one of an array of majority vote circuits, whereby the output of said array of majority vote circuits comprises the corrected code.

Claim 3

The circuitry of claim 1 wherein the relationship of said original and redundant bytes is expressed as, y n =x n ⊕x n+1 , and wherein each byte contains eight binary bits, and the number of said modulo 2 adders per array and the number of majority vote circuits per array is eight.

Claim 4

Apparatus for error correction of binary digital codes recalled from memory comprising means providing for 100% memory redundancy whereby an original and redundant byte are stored in memory and wherein said redundant byte is generated by logic circuitry to which said original byte is applied, further logic circuitry arranged to produce two new bytes from the said original and redundant bytes as recalled from memory, and majority vote logic circuitry for receiving said two new bytes and said original byte as recalled from memory and producing a corrected code comprising the majority vote of the corresponding digits of said two new bytes and said original byte as recalled from memory.

Claim 5

Apparatus for error correction of binary digital codes recalled from memory comprising means providing for 100% memory redundancy whereby an original and redundant byte are stored in memory and wherein said redundant byte is generated by logic circuitry to which said original byte is applied, further logic circuitry arranged to produce two new bytes from the said original and redundant bytes as recalled from memory, and majority vote logic circuitry for receiving said two new bytes and said original byte as recalled from memory and producing a corrected code comprising the majority vote of the corresponding digits of said two new bytes and said original byte as recalled from memory.

Claim 6

The apparatus of claim 3 wherein said majority vote logic circuitry comprises an array of majority vote circuits, one majority vote circuit for each bit per byte, and whereby the output of said array comprises the original code as corrected.

Claim 7

The apparatus of claim 3, further comprising means to transpose said original and redundant bytes before storage in memory and means to similarly re-transpose said bytes upon recall from memory before application to said further logic.

Claim 10

Error correction circuitry comprising, means to generate a redundant byte, y 7 -y 0 , for each original byte, x 7 -x 0 , wherein y n =x n ⊕x n+1 , and means to transpose the bits of both said bytes so that the x and y bits are alternated, means to store said original and redundant transposed bytes in memory, means to recall said transposed bytes from memory and means to re-transpose them to their original sequence, and means to apply said re-transposed original and redundant recalled bytes to a decoder circuit comprising two arrays of modulo 2 adders which produce two new bytes represented as x b7 -x b0 and x c7 -x c0 , and means to apply said two new bytes plus said original recalled byte to an array of majority vote circuits, the output of said majority vote circuits comprising the original corrected code, whereby burst errors of up to two bits in the bytes as recalled from memory may be corrected.

Claim 11

Error correction circuitry comprising, means to generate a redundant byte, y 7 -y 0 , for each original byte, x 7 -x 0 , wherein y n =x n ⊕x n+1 , and means to transpose the bits of both said bytes so that the x and y bits are alternated, means to store said original and redundant transposed bytes in memory, means to recall said transposed bytes from memory and means to re-transpose them to their original sequence, and means to apply said re-transposed original and redundant recalled bytes to a decoder circuit comprising two arrays of modulo 2 adders which produce two new bytes represented as x b7 -x b0 and x c7 -x c0 , and means to apply said two new bytes plus said original recalled byte to an array of majority vote circuits, the output of said majority vote circuits comprising the original corrected code, whereby burst errors of up to two bits in the bytes as recalled from memory may be corrected.

Claim 12

The circuit of claim 7 wherein x bn =x a (n+1) ⊕y an and x cn =x a (n-1) ⊕y a (n-1).