Patent US4564875A successfully refreshed from Google Patents.
Patent US5024959A successfully refreshed from Google Patents.
US5024959A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS process using doped glass layer
Assignee: Motorola Solutions Inc
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Filing: 1989-09-25
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Granted: 1991-06-18
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Expires: 2009-09-25
Abstract
Abstract An improved LDD CMOS fabrication is disclosed which uses a reduced number of processing steps. In accordance with one embodiment of the invention, a silicon substrate is provided which has first and second surface regions of opposite conductivity type. First and second silicon gate electrodes overlie the first and second surface regions, respectively. A dopant source layer containing dopant impurities of the first conductivity type is deposited over the first and second gate electrodes. This dopant source layer is patterned to form sidewall spacers at the edges of the first silicon gate electrode. Those sidewall spacers are used in the formation of the LDD structure on the devices formed in the first surface region. After removing the sidewall spacers, the structure is heated to diffuse dopant impurities from the dopant source layer into the second surface region to form source and drain regions of transistors formed in that region. The only lithography step needed in this portion of the process is one to protect the dopant source layer over the second region while sidewall spacers are being formed in the first region.
Inventors
- 👤 James R. Pfiester
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
152 words
A method for fabricating a CMOS integrated device comprising the steps of: providing a silicon substrate having a first surface region of first conductivity type and a second surface region of second conductivity type; forming a first silicon gate electrode overlying said first surface region and a second silicon gate electrode overlying said second surface region; depositing a dopant source layer containing dopant impurities of said first conductivity type overlying said first and second silicon gate electrodes; patterning said dopant source layer overlying said first silicon gate electrode to form sidewall spacers at edges of said first silicon gate electrode; doping portions of said first surface region with conductivity determining dopant impurities of said second conductivity type using said sidewall spacers as dopant masks; and heating said dopant source layer to diffuse dopant impurities therefrom to dope portions of said second surface region with conductivity determining dopant of said first conductivity type.
Claim 2
Independent Claim
152 words
A method for fabricating a CMOS integrated device comprising the steps of: providing a silicon substrate having a first surface region of first conductivity type and a second surface region of second conductivity type; forming a first silicon gate electrode overlying said first surface region and a second silicon gate electrode overlying said second surface region; depositing a dopant source layer containing dopant impurities of said first conductivity type overlying said first and second silicon gate electrodes; patterning said dopant source layer overlying said first silicon gate electrode to form sidewall spacers at edges of said first silicon gate electrode; doping portions of said first surface region with conductivity determining dopant impurities of said second conductivity type using said sidewall spacers as dopant masks; and heating said dopant source layer to diffuse dopant impurities therefrom to dope portions of said second surface region with conductivity determining dopant of said first conductivity type.
Claim 3
Dependent Claim
45 words
The method of claim 1 further comprising the steps of forming a layer of oxide overlying edges of said first and second gate electrodes and depositing a layer of polycrystalline silicon overlying said layer of oxide before said step of depositing a dopant source layer.
Claim 4
Independent Claim
168 words
A method for fabricating a CMOS integrated device comprising the steps of: providing a silicon substrate having a first surface region of first conductivity type and a second surface region of second conductivity type; forming a first silicon gate electrode overlying said first surface region and a second silicon gate electrode overlying said second surface region; depositing a dopant source layer containing dopant impurities of said first conductivity type overlying said first and second silicon gate electrodes; forming a mask overlying said second surface region to protect the dopant source layer thereunder; anisotropically etching said dopant source layer overlying said first silicon gate electrode to form sidewall spacers at edges of said first silicon gate electrode; doping portions of said first surface region with conductivity determining dopant impurities of said second conductivity type using said sidewall spacers as dopant masks; and heating said dopant source layer to diffuse dopant impurities therefrom to dope portions of said second surface region with conductivity determining dopant of said first conductivity type
Claim 5
Independent Claim
168 words
A method for fabricating a CMOS integrated device comprising the steps of: providing a silicon substrate having a first surface region of first conductivity type and a second surface region of second conductivity type; forming a first silicon gate electrode overlying said first surface region and a second silicon gate electrode overlying said second surface region; depositing a dopant source layer containing dopant impurities of said first conductivity type overlying said first and second silicon gate electrodes; forming a mask overlying said second surface region to protect the dopant source layer thereunder; anisotropically etching said dopant source layer overlying said first silicon gate electrode to form sidewall spacers at edges of said first silicon gate electrode; doping portions of said first surface region with conductivity determining dopant impurities of said second conductivity type using said sidewall spacers as dopant masks; and heating said dopant source layer to diffuse dopant impurities therefrom to dope portions of said second surface region with conductivity determining dopant of said first conductivity type
Claim 6
Dependent Claim
66 words
The method of claim 3 wherein said step of doping portions of said first surface region comprises: implanting ions of said second conductivity type into said first surface region using said sidewall spacers and said mask as ion implant masks; removing said sidewall spacers; and implanting said first surface region with additional ions of said second conductivity type using said mask as an ion implantation mask.
Claim 7
Dependent Claim
36 words
The method of claim 3 wherein said step of depositing a dopant source layer comprises the steps of forming an impurity doped glass layer; and depositing an undoped glass layer overlying said impurity doped glass layer.
Claim 8
Dependent Claim
24 words
The method of claim 5 wherein said step of patterning said dopant source layer further comprises the step of patterning said undoped glass layer.
Claim 9
Dependent Claim
30 words
The method of claim 6 further comprising the step of removing said dopant source layer and said undoped glass layer overlying said first surface region before said step of heating.
Claim 10
Independent Claim
268 words
A method for fabricating a CMOS integrated circuit device comprising the steps of; providing a silicon substrate having a first surface region of first conductivity type and a second surface region of second conductivity type; forming a first silicon gate electrode overlying said first surface region and a second silicon gate electrode overlying said second surface region; forming a layer of silicon oxide overlying edges of said first and second silicon gate electrodes; depositing a layer of undoped silicon overlying said layer of silicon oxide; depositing a dopant source layer containing dopant impurities of said first conductivity type overlying said layer of undoped silicon; depositing an undoped insulator layer overlying said dopant source layer; forming a photoresist mask overlying said surface region of second conductivity type; anisotropically etching said dopant source layer and said undoped insulator layer overlying said surface region of first conductivity type to form sidewall spacers at the edges of said first silicon gate electrode; implanting ions of second conductivity type into said first surface region using said sidewall spacers and said photoresist mask as implantation masks; removing said sidewall spacers; implanting additional ions of second conductivity type into said first surface region using said first silicon gate electrode and said photoresist mask as implantation masks; removing said photoresist mask; heating said dopant source layer to diffuse dopant impurities therefrom into said second surface region; removing remaining portions of said dopant source layer and said layer of silicon oxide using said layer of undoped silicon as an etch stop; and heating in an oxidizing ambient to convert said layer of undoped silicon to silicon dioxide.
Claim 11
Independent Claim
268 words
A method for fabricating a CMOS integrated circuit device comprising the steps of; providing a silicon substrate having a first surface region of first conductivity type and a second surface region of second conductivity type; forming a first silicon gate electrode overlying said first surface region and a second silicon gate electrode overlying said second surface region; forming a layer of silicon oxide overlying edges of said first and second silicon gate electrodes; depositing a layer of undoped silicon overlying said layer of silicon oxide; depositing a dopant source layer containing dopant impurities of said first conductivity type overlying said layer of undoped silicon; depositing an undoped insulator layer overlying said dopant source layer; forming a photoresist mask overlying said surface region of second conductivity type; anisotropically etching said dopant source layer and said undoped insulator layer overlying said surface region of first conductivity type to form sidewall spacers at the edges of said first silicon gate electrode; implanting ions of second conductivity type into said first surface region using said sidewall spacers and said photoresist mask as implantation masks; removing said sidewall spacers; implanting additional ions of second conductivity type into said first surface region using said first silicon gate electrode and said photoresist mask as implantation masks; removing said photoresist mask; heating said dopant source layer to diffuse dopant impurities therefrom into said second surface region; removing remaining portions of said dopant source layer and said layer of silicon oxide using said layer of undoped silicon as an etch stop; and heating in an oxidizing ambient to convert said layer of undoped silicon to silicon dioxide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-17 | 1994-12-17 | 1995-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-17 | 1998-12-17 | 1999-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-17 | 2002-12-17 | 2003-06-18 | $7700.00 | Window Closed / Lapsed |