Automatic sizing memory system with multiplexed configuration signals at memory modules

Claim 2

An automatic sizing memory system for transferring memory data to and from a processor and receiving addresses and commands from said processor, said memory system comprising: memory controller means for generating information to form a configuration structure representing the arrangement of storage locations in said memory system and for forming memory addresses and memory select signals from the addresses and commands received from said processor, said memory controller means including configuration register means for storing said configuration structure according to configuration data descriptive of the arrangement of storage locations in said memory system, and control logic for forming the memory addresses and memory select signals from the addresses and commands received from said processor and from the configuration structure stored in the configuration register means; a memory bus, coupled to said memory controller means and carrying memory data, the memory addresses, and the memory select signals; and a first number of memory modules coupled to the memory bus and each of said memory modules including storage means, coupled to the memory bus and having one of a plurality of configurations, for storing memory data at and for retrieving stored memory data from different locations corresponding to the memory addresses on the memory bus, signature means for storing configuration data identifying the configuration of said storage means, multiplexer means, having inputs coupled to said storage means and said signature means and having an output coupled to said memory bus, for placing, when activated, either the memory data or the configuration data onto said memory bus in response to multiplex control signals; and control means, coupled to said multiplexer means and said memory bus, for activating said multiplexer means and for generating the multiplex control signals from the memory addresses and memory select signals on said memory bus thereby causing said multiplexer when activated, to transfer either the memory data or the configuration data onto the memory bus.

Claim 3

The automatic sizing memory system of claim 1 wherein for each of said modules said storage means include at least one bank of memory cells, and wherein said signature means includes means for storing the configuration data identifying the number of banks in said storage means and the size of said banks.

Claim 4

The automatic sizing memory system of claim 1 wherein for each of said modules said multiplexer means includes a plurality of transceivers coupled to the memory bus, and a plurality of multiplexers having one set of inputs coupled to the at least one bank of memory cells and another set of inputs coupled to said signature means; and wherein said control means includes means for forming a multiplex control signal for activating said plurality of transceivers, and means for forming a second multiplex control signal to select one of the sets of inputs.

Claim 5

The automatic sizing memory system of claim 1 wherein said memory bus includes an address bus carrying the memory addresses and memory select signals and a memory data bus carrying the memory data and the configuration data.

Claim 6

The automatic sizing memory system of claim 1 wherein for each of said modules said signature means includes means for storing configuration data identifying a type of error detection for the memory data.

Claim 7

The automatic sizing memory system of claim 1 wherein said configuration register means includes means for specifying that configuration data for selected ones of the memory modules should be read from the signature means.

Claim 8

The automatic sizing memory system of claim 6 wherein said specifying means in said configuration register means includes a bit set by the processor.

Claim 9

The automatic sizing memory system of claim 1 wherein each said storage means includes at least one bank of memory cells and wherein said configuration register means includes a plurality of status register means each corresponding to a different one of said at least one memory bank and each containing a base address data identifying the starting address of each of said at least one memory banks.

Claim 10

The automatic sizing memory system of claim 8 wherein each of said status register means includes means for indicating when the base address data in the status register for the corresponding memory bank is valid.

Claim 11

The automatic sizing memory system of claim 8 wherein said status register means each include means for comparing the addresses received from said processor to the base addresses data in that status register means to select the ones of said at least one memory banks containing locations corresponding to each of those addresses, and means for activating address selection signals identifying the selected memory banks.

Claim 12

The automatic sizing memory system of claim 10 wherein said memory bus includes address selection lines containing the memory select signals, and wherein said control logic includes means for enabling certain of the memory select signals on said address selection lines according to the activated address selection signals.

Claim 13

The automatic sizing memory system of claim 10 wherein each of said status register means includes means for enabling an address hit signal from the activated address selection signals to indicate when addresses from the processor are within one of said memory banks.

Claim 14

The automatic sizing memory system of claim 8 wherein each of said status register means includes means for indicating when memory data read from the corresponding memory bank contains an error.

Claim 15

The automatic sizing memory system of claim 8 wherein each of said status register means includes means for indicating the size of the corresponding memory bank.

Claim 16

The automatic sizing memory system of claim 8 wherein each of said status register means includes means for locking out access to the corresponding memory bank.

Claim 17

The automatic sizing memory system of claim 1 further including error detecting means, coupled to said memory bus, for detecting errors in the memory data.

Claim 18

The automatic sizing memory system of claim 18 further including at least one first memory connector and at least one second memory connector connected to said memory bus, said at least one first memory connector each corresponding to and being connected to a different one of said memory modules, and said at least one second memory connector not being connected to any of said memory modules; and wherein said memory controller means includes means for obtaining configuration data for said at least one second memory connector indicating that no memory module is coupled to said at least one second memory connector.

Claim 19

The automatic sizing memory system of claim 1 wherein each of said storage means includes at least one bank of memory cells, and wherein said configuration register means includes a plurality of status register each corresponding to a different one of the at least one memory bank and each of said status registers including configuration read data specifying a configuration read operation of the configuration data for the corresponding memory bank, and wherein said control means includes means for responding to said configuration read data to enable said memory select signals to cause the multiplexer means for the corresponding memory bank to place the configuration data for the corresponding memory bank onto said memory data bus.

Claim 20

A data processing system for automatic memory configuration and initialization comprising; a central processing unit; booting means, coupled to said central processing unit, for causing said central processing unit to institute memory initialization procedures including the generation of commands and addresses; and a memory system, coupled to said central processing unit and responsive to the initialization procedures, said memory system including memory controller means for generating information to form a configuration structure representing the arrangement of storage locations in said memory system and for forming memory addresses and memory select signals from addresses and commands received from said central processing unit, said memory controller means including configuration register means for storing said configuration structure according to configuration data descriptive of the arrangement of storage locations in said memory system, and control logic for forming the memory addresses and memory select signals from the addresses and commands received from said processor and from the configuration structure stored in the configuration register means; a memory bus, coupled to said memory controller means, for carrying memory data, the memory addresses, and the memory select signals; and a first number of memory modules coupled to the memory bus and each including storage means, coupled to the memory bus and having one of a plurality of configurations, for storing memory data at and for retrieving stored memory data from different locations corresponding to the memory addresses on the memory bus, signature means for storing configuration data identifying the configuration of said storage means, multiplexer means, having inputs coupled to said storage means and said signature means and having an output coupled to said memory bus, for placing, when activated, either the memory data or the configuration data onto said memory bus in response to multiplex control signals; and control means, coupled to said multiplexer means and said memory bus, for activating said multiplexer means and for generating the multiplex control signals from the memory select signals on said memory bus thereby causing said multiplexer means, when activated, to transfer either the memory data or the configuration data onto said memory bus.

Claim 21

A data processing system for automatic memory configuration and initialization comprising; a central processing unit; booting means, coupled to said central processing unit, for causing said central processing unit to institute memory initialization procedures including the generation of commands and addresses; and a memory system, coupled to said central processing unit and responsive to the initialization procedures, said memory system including memory controller means for generating information to form a configuration structure representing the arrangement of storage locations in said memory system and for forming memory addresses and memory select signals from addresses and commands received from said central processing unit, said memory controller means including configuration register means for storing said configuration structure according to configuration data descriptive of the arrangement of storage locations in said memory system, and control logic for forming the memory addresses and memory select signals from the addresses and commands received from said processor and from the configuration structure stored in the configuration register means; a memory bus, coupled to said memory controller means, for carrying memory data, the memory addresses, and the memory select signals; and a first number of memory modules coupled to the memory bus and each including storage means, coupled to the memory bus and having one of a plurality of configurations, for storing memory data at and for retrieving stored memory data from different locations corresponding to the memory addresses on the memory bus, signature means for storing configuration data identifying the configuration of said storage means, multiplexer means, having inputs coupled to said storage means and said signature means and having an output coupled to said memory bus, for placing, when activated, either the memory data or the configuration data onto said memory bus in response to multiplex control signals; and control means, coupled to said multiplexer means and said memory bus, for activating said multiplexer means and for generating the multiplex control signals from the memory select signals on said memory bus thereby causing said multiplexer means, when activated, to transfer either the memory data or the configuration data onto said memory bus.

Claim 22

The data processing system in claim 19 wherein said booting means includes a ROM including a memory initialization program containing instructions to implement the memory initialization procedures, and means for sensing an initialization condition to cause said central processing unit to begin the initialization program.

Claim 23

The data processing system in claim 20 wherein said ROM also includes initialization programs for other portions of said data processing system.

Claim 24

The data processing system of claim 19 wherein for each module each of said storage means includes at least one bank of memory cells, and wherein said signature means includes means for storing the configuration data identifying the number and size of banks.

Claim 25

The data processing system of claim 22 wherein for each of said modules said multiplexer means includes a plurality of transceivers coupled to the memory bus, and a plurality of multiplexers having one set of inputs coupled to the at least one bank of memory cells and another set of inputs coupled to said signature means; and wherein said control means includes means for forming a first multiplex control signal for activating said plurality of transceivers, and means for forming a second multiplex control signal to select one of the sets of inputs.

Claim 26

The data processing system of claim 19 wherein said memory bus includes an address bus carrying the memory addresses and memory select signals and a memory data bus carrying the memory data and the configuration data.

Claim 27

The data processing system of claim 19 wherein for said modules said signature means includes means for storing configuration data identifying a type of error detection for the memory data.

Claim 28

The data processing system of claim 19 wherein each of said configuration register means includes means for specifying that configuration data for the corresponding memory bank should be read from the signature means.

Claim 29

The data processing system of claim 26 wherein said specifying means in said configuration register means includes a bit set by the processor.

Claim 30

The data processing system of claim 19 wherein for each of said modules said storage means includes at least one bank of memory cells, and wherein said configuration register means includes a plurality of status register means each corresponding to a different one of said at least one memory bank and each containing base address data identifying the address of each of said at least one memory bank.

Claim 31

The data processing system of claim 28 wherein each of said status register means also includes means for indicating when the base address data in the status register for the corresponding memory bank is valid.

Claim 32

The data processing system of claim 28 wherein said status register means each include means for comparing the addresses received from said processor to the base address data in that status register means to select the ones of said memory banks containing locations corresponding to each of those addresses, and means for activating address selection signals identifying the selected memory banks.

Claim 33

The data processing system of claim 30 wherein said memory bus includes address selection lines carrying the memory select signals, and wherein said control logic includes means for enabling the memory select signals on said address selection lines based on the activated address selection signals.

Claim 34

The data processing system of claim 30 wherein each of said status register means includes means for enabling an address hit signal from the activated address selection signals to indicate when addresses from the processor are within one of said memory banks.

Claim 35

The data processing system of claim 28 wherein each of said status register means includes means for indicating when memory data read from the corresponding memory bank contains an error.

Claim 36

The data processing system of claim 28 wherein each of said status register means includes mean for indicating the size of the corresponding memory bank.

Claim 37

The data processing system of claim 28 wherein each of said status register means includes means for locking out access to the corresponding memory bank.

Claim 38

The data processing system of claim 19 further including error detecting means, coupled to said memory bus, for detecting errors in the memory data.

Claim 39

The data processing system of claim 19 further including at least one first memory connector and at least one second memory connector connected to said memory bus, said at least one first memory connector each corresponding to and being connected to a different one of said memory modules, and said at least one second memory connector not being connected to any of said memory modules; and wherein said memory controller means includes means for obtaining configuration data for said at least one second memory connector indicating that no memory module is coupled to said at least one second memory connector.

Claim 40

The data processing system of claim 19 wherein in each of said modules said storage means includes at least one bank of memory cells, and wherein said configuration register means includes a plurality of status registers each corresponding to a different one of the at least one memory banks, each of said status registers including configuration read data specifying a read of the configuration data for the corresponding memory bank, and wherein said control means includes means for responding to said configuration read data to form said memory select signals to cause the multiplexer means in the corresponding memory bank to place the configuration data for the corresponding memory bank onto said memory data bus.