US4393443A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory mapping system
Assignee: Tektronix Inc
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Filing: 1980-05-20
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Granted: 1983-07-12
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Expires: 2000-05-20
Abstract
Abstract A circuit for enhancing the performance of a random-access-memory-based memory expansion system is disclosed. Memory capacity and a control register are added to the traditional memory mapping circuit. The increased memory is utilized to store several maps simultaneously and the circuit output is then switched from one stored map to another according to data present at the control register outputs. Thus, by pre-loading the circuit with all the memory maps required by a particular program, delay caused by map changes is reduced to the time required to move data to the control register outputs.
Inventors
- 👤 John Lewis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:43
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
232 words
A memory mapping system comprising: a first address bus portion having a first set of n lines and a second set of x lines, for receiving logical address information; a second address bus portion for providing physical address information to main memory means of a computer, said second address bus portion having a first set of N lines, where N is greater than n, and a second set of x lines connected to the second set of x lines of the first address bus portion; random access memory means having n input lines connected to the first set of n lines of the first address bus portion and N output lines connected to the first set of N lines of the second address bus portion, said random access memory means having a plurality of memory regions which are individually selectable for connection to said n input lines and to said N output lines, and each memory region being operative, when selected, to transform information provided on said n input into information on said N output lines; and a control register having input means for receiving data and output means at which said data is made available and operatively connected to the random access memory means for utilizing said data to select which one of the plurality of memory regions is connected to said n input lines and to said N output lines.
Claim 2
Dependent Claim
232 words
A memory mapping system comprising: a first address bus portion having a first set of n lines and a second set of x lines, for receiving logical address information; a second address bus portion for providing physical address information to main memory means of a computer, said second address bus portion having a first set of N lines, where N is greater than n, and a second set of x lines connected to the second set of x lines of the first address bus portion; random access memory means having n input lines connected to the first set of n lines of the first address bus portion and N output lines connected to the first set of N lines of the second address bus portion, said random access memory means having a plurality of memory regions which are individually selectable for connection to said n input lines and to said N output lines, and each memory region being operative, when selected, to transform information provided on said n input into information on said N output lines; and a control register having input means for receiving data and output means at which said data is made available and operatively connected to the random access memory means for utilizing said data to select which one of the plurality of memory regions is connected to said n input lines and to said N output lines.
Claim 3
Dependent Claim
79 words
A memory mapping system according to claim 1, wherein said random access memory means comprise a single random access memory (RAM) and each memory region constitutes an independent set of addressable memory locations in the RAM, said RAM having m additional input lines connected to the output means of the control register, whereby the control register is able to select each of said independent sets of memory locations in dependence upon data received by way of said input means.
Claim 4
Dependent Claim
113 words
A memory mapping system according to claim 1, wherein said random access memory means comprise a plurality of random access memories (RAMs) each having n input lines connected to the first set of n lines of the first address bus portion and N output lines connected to the first set of N lines of the second address bus portion, and each RAM also has an output enable terminal, and said control register has a plurality of output terminals connected to the output enable terminals of the RAMs respectively, whereby the control register is able to enable the output lines of each RAM in dependence upon data received by way of said input means.
Claim 5
Dependent Claim
122 words
A memory mapping system according to claim 1, wherein said random access memory means comprise a plurality of random access memories (RAMs) each having n input lines connected to the first set of n lines of the first address bus portion and N output lines, and multiplexing means connected to the N output lines of the RAMs, said multiplexing means being operative to transfer information provided on the N output lines of a selected RAM to the N output lines of said random access memory means, and having control input means connected to the output means of the control register for effecting selection of a RAM in dependence upon data received by the control register by way of said input means thereof.
Claim 6
Dependent Claim
49 words
A memory mapping system according to claim 1, wherein said control register comprises a data register capable of being loaded by way of said input means with data for presentation at said output means and for maintaining said data at said output means for a desired length of time.
Claim 7
Dependent Claim
19 words
A memory mapping system according to claim 5, wherein said data register is a first in, first out register.
Claim 8
Dependent Claim
16 words
A memory mapping system according claim 5, wherein said data register is a random access memory.
Claim 9
Dependent Claim
16 words
A memory mapping system according to claim 5, wherein said data register is a shift register.
Claim 10
Dependent Claim
64 words
A computer comprising a memory mapping system according to claim 1, 2, 3, or 4, a processor unit having (n+x) address lines connected to said first address bus portion for applying logical address information to the memory mapping system, and main memory means having (N+x) address lines connected to said second address bus portion for receiving physical address information from the memory mapping system.
Claim 11
Dependent Claim
195 words
A memory mapping system comprising: a first address bus portion having a first set of n lines and a second set of x lines, for receiving logical address information; a second address bus portion for providing physical address information to main memory means of a computer, said second address bus portion having a first set of N lines, where N is greater than n, and a second set of x lines connected to the second set of x lines of the first address bus portion; and random access memory means having n input lines connected to the first set of n lines of the first address bus portion and N output lines connected to the first set of N lines of the second address bus portion, said random access memory means being operative to transform information provided on said n input lines into information on said N output lines, and the random access memory means also having a load data input for loading data into the random access memory means, whereby the information that is provided on said N output lines in response to given information provided on said n input lines may be altered.
Claim 12
Dependent Claim
195 words
A memory mapping system comprising: a first address bus portion having a first set of n lines and a second set of x lines, for receiving logical address information; a second address bus portion for providing physical address information to main memory means of a computer, said second address bus portion having a first set of N lines, where N is greater than n, and a second set of x lines connected to the second set of x lines of the first address bus portion; and random access memory means having n input lines connected to the first set of n lines of the first address bus portion and N output lines connected to the first set of N lines of the second address bus portion, said random access memory means being operative to transform information provided on said n input lines into information on said N output lines, and the random access memory means also having a load data input for loading data into the random access memory means, whereby the information that is provided on said N output lines in response to given information provided on said n input lines may be altered.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-11 | 1987-01-10 | 1987-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-11 | 1991-01-10 | 1991-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-11 | 1995-01-10 | 1995-07-12 | $7700.00 | Window Closed / Lapsed |