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US3949378A
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Computer memory addressing employing base and index registers
Assignee: United States Department of the Navy
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Filing: 1974-12-09
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Granted: 1976-04-06
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Expires: 1994-12-09
Abstract
Abstract A memory addressing system which enables a computer to address a total of 1,048,575 words (32 times its original capacity) with minimal impact upon existing software. The method employed by this invention involves a new dual usage of the b (index) designator in each instruction word so that in addition to its normal function of specifying which of 8 index registers is to be added to the address portion of the instruction, it also specifies which of 8 base registers is to be arithmetically added to the basic 15-bit address to determine the final 20-bit absolute memory location address. A total of 262,144 words may be accessed by this dual use of the b designator for any one setting of the base registers. Each program module is designed to operate in a 32,768 word environment and no coding changes need be made to it; the computer operator need only maintain the appropriate offset values in the base registers for the module currently in operation.
Inventors
- 👤 Robert P. Crabb
- 👤 Robert A. Unger
- 👤 Jim A. Gilbreath
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:20
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292; G06F12/06; G06F12/0615; G06F12/0623
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
272 words
A system for computer memory addressing which permits accessing to an original, internal, memory of a computer whose capacity in words is no longer adequate as well as to an additional, external, memory which extends the capacity to an adequate level, the system comprising: means for accessing an instruction word generated by the internal memory, the word including an M-bit index designator and an N-bit operand address designator; an index register, each of whose cells have the capability of containing N bits; a base register, each of whose cells have the capability of containing N + K bits, for offsetting all addresses in a given class by a given amount; means connected to the accessing means to receive the index designator for simultaneously accessing corresponding cells in the index and base registers; a first adder, coupled to receive the operand address designator and the accessed signal of the index register; a second adder, coupled to receive the output signal of the first adder and the accessed signal of the base register; and; a comparator, whose input is the output of the second adder, which compares the magnitude of the address of the instruction word with the magnitude of a word generated within the comparator representing the capacity of the original internal memory, and generates an output signal which is alternatively directed to 1. the internal memory if the magnitude of the address of the instruction word is at least equal to the capacity of the internal memory; and 2. to the external memory if the magnitude of the address of the instruction word is greater than the capacity of the internal memory.
Claim 2
Independent Claim
272 words
A system for computer memory addressing which permits accessing to an original, internal, memory of a computer whose capacity in words is no longer adequate as well as to an additional, external, memory which extends the capacity to an adequate level, the system comprising: means for accessing an instruction word generated by the internal memory, the word including an M-bit index designator and an N-bit operand address designator; an index register, each of whose cells have the capability of containing N bits; a base register, each of whose cells have the capability of containing N + K bits, for offsetting all addresses in a given class by a given amount; means connected to the accessing means to receive the index designator for simultaneously accessing corresponding cells in the index and base registers; a first adder, coupled to receive the operand address designator and the accessed signal of the index register; a second adder, coupled to receive the output signal of the first adder and the accessed signal of the base register; and; a comparator, whose input is the output of the second adder, which compares the magnitude of the address of the instruction word with the magnitude of a word generated within the comparator representing the capacity of the original internal memory, and generates an output signal which is alternatively directed to 1. the internal memory if the magnitude of the address of the instruction word is at least equal to the capacity of the internal memory; and 2. to the external memory if the magnitude of the address of the instruction word is greater than the capacity of the internal memory.
Claim 3
Dependent Claim
34 words
The computer memory addressing system according to claim 1, further comprising: means for connecting the base register to an accumulator register of the computer for writing into and reading out of the base register.
Claim 4
Dependent Claim
33 words
The computer memory addressing system according to claim 1, further comprising: means for connecting the base register to the input-output channel of the computer for extending the input and output of the computer.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-04-06 | 1979-10-06 | 1980-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-04-06 | 1983-10-06 | 1984-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-04-06 | 1987-10-06 | 1988-04-06 | $7700.00 | Window Closed / Lapsed |