Data processing devices using capability registers

Claim 1

In a time-sharing data processing system including a central memory adapted to store information in segments and at least one processing unit including a plurality of capability register means each arranged to store segment descriptor information indicative of the base and limit memory addresses of an information segment together with access-type information indicative of the permitted mode of access which may be used to the segment defined by the base and limit addresses, each said processing unit including means for performing a load capability register instruction whose instruction word contains information defining (a) the identity of a capability register means to be loaded, (b) the identity of a first one of said capability register means and (c) an offset value, the improvement comprises in combination (i) a first one of said capability register means for holding a first segment descriptor relative to an information segment which contains a reserved segment pointer table particular to a program currently being executed by said processing unit, (ii) a second one of said capability register means so holding a second segment descriptor relative to an information segment which contains a master capability table, said master capability table having an entry for each information segment in said central memory, each entry including information defining the base and limit addresses of a segment, said reserved segment pointer table including a list of data words which are used as pointers to define different entries in said master capability table, each of said data words in said reserved segment pointer table being accompanied by permitted access-type information, and (iii) capability register loading means comprising; first means for forming an address of a pointer word in said reserved segment pointer table by adding said offset value to the base address held in said first one of said capability register means; second means for reading a data word from the formed address in said reserved pointer table; third means for inserting the permitted access type information read from said pointer word into said capability register means to be loaded; fourth means for forming an entry address in said master capability table by adding the pointer word read from said reserved pointer table to the base address held in the said second one of said capability register means; and fifth means for reading the base and limit information from the entry addressed by said fourth means in said master capability table into the capability register means to be loaded.