EP0193210A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device with a built-in test circuit
Assignee: NEC Corp
•
Filing: 1986-02-28
•
Granted: —
•
Expires: 2006-02-28
Abstract
Abstract A semiconductor memory device which has an on-chip test circuit as disclosed. The memory device has a plurality of memory cells. The on-chip test circuit includes a test write circuit for writing the same write data to at least two sefected memory cells, a read circuit for simultaneously reading stored data from at least two selected memory cells and a comparison circuit for comparing date read from the at least two memory cells. The comparison result by the comparator circuit show whether at least one of the at least two selected memory cells is bad, or all of the at least two selected memory cells are good.
Inventors
- 👤 Naoki Katanosaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 20:49
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
52 words
A memory device comprising a plurality of memory cells, first means for operatively writing a predetermined logic data to at least two memory cells simultaneously, second means for reading data stored in said at least two memory cells and third means for comparing data read from said at least two memory cells.
Claim 2
Dependent Claim
52 words
A memory device comprising a plurality of memory cells, first means for operatively writing a predetermined logic data to at least two memory cells simultaneously, second means for reading data stored in said at least two memory cells and third means for comparing data read from said at least two memory cells.
Claim 3
Dependent Claim
37 words
The memory device according to claim 1, in which said memory cells are arranged in at least two memory cell arrays, and one of memory cell is selected for writing or reading in each of said arrays.
Claim 4
Dependent Claim
25 words
The memory device according to claim 1, in which said comparison circuit includes an Exclusive-OR circuit receiving data from selected memory cells of said arrays.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.