Parasitic memory expansion for computers

Claim 2

In a digital computer having at least one addressable memory bank for storing data signals therein, each said addressable memory bank having multiple circuit connectors for address and control signals to store and retrieve said data signals including one of said multiple circuit connectors from which said addressable memory bank has been removed, the improvement comprising: (a) a memory expansion circuit including a plurality of expansion memory banks, said expansion memory banks electrically connected in parallel to one another and one of said expansion memory banks connected to said one of said multiple connectors from which said addressable memory bank has been removed, each said expansion memory bank corresponding to said addressable memory banks in said digital computer; (b) logic control means connected in parallel to said plurality of expansion memory banks and having first and second operating modes; (c) a plurality of input/output means interconnecting said plurality of expansion memory banks and said one multiple circuit connector for operationally connecting said address and control signals to said expansion memory banks; (d) said logic control means having digital decoder means responsive to a predetermined combination of said data, address and control signals to operate in said first operating mode and to select and make operational a particular one of said plurality of expansion memory banks in which information is to be stored; and (e) said logic control means operating in said second mode in the absence of said predetermined combination of signals to enable said data signals to be stored in and retrieved from said expansion memory bank selected by said digital decoder means to be operational in said first operational mode, said digital decoder means including an N-bit latch for inserting and storing said predetermined combination of said data signals when said logic control means is in said first operating mode, and for retaining said predetermined combination of said data signals when said logic control means is in said second operating mode.

Claim 3

In a digital computer according to claim 1, wherein said addressable memory banks and said expansion banks are defined by dynamic random access memory devices.

Claim 4

In a digital computer according to claim 1 wherein each of said expansion banks is connected in parallel to said computer via said one multiple circuit connector, and said data signals, address signals and control signals are all inputted via the pre-existing connections to said one multiple circuit connector, thereby implementing a totally parasitic memory expansion for said computer.

Claim 5

In a digital computer according to claim 1 wherein said digital decoder further comprises an N-line-to-M-line logic decoder connected to said N-bit latch for decoding said predetermined combination of data signals and for producing a selection signal for selecting and making operational said particular one of said expansion memory banks.

Claim 6

In a data processing unit having memory devices for storing data signals arranged in a plurality of addressable memory banks, each said addressable memory bank connectable to a multiple circuit connection for address and control signals to store and retrieve said data signals and having one multiple circuit connection from which one of said addressable memory banks has been removed, the combination therewith of a memory expansion circuit comprising: (a) a plurality of expansion memory banks each having a plurality of expansion memory devices arranged in a row, said rows of expansion memory devices electrically connected in parallel to one another and one row of said expansion memory devices connected to said one multiple circuit connection from which said one addressable memory bank has been removed, each said expansion bank corresponding to each said addressable memory bank in said digital computer; (b) logic control means connected to said plurality of expansion memory banks and having first and second operating modes; (c) input/output means operationally connecting said multiple circuit connections of said one row of said addressable memory devices to said plurality of expansion memory banks and to said logic control means; (d) said logic control means responsive to said address and control signals to said one row of addressable memory deviced to operate in said first mode to select and make operational a particular one of said plurality of expansion memory banks; and (e) said logic control means operating in said second mode in the absence of said predetermined combination of signals to enable said data signals to be stored in and retrieved from said expansion memory bank selected by said digital decode means to be operational in said first operational mode, said digital decoder means including an N-bit latch for inserting and storing said predetermined combination of said data signals when said logic control means is in said first operating mode, and for retaining said predetermined combination of said data signals when said logic control means is in said second operating mode.

Claim 7

In a data processing unit having memory devices for storing data signals arranged in a plurality of addressable memory banks, each said addressable memory bank connectable to a multiple circuit connection for address and control signals to store and retrieve said data signals and having one multiple circuit connection from which one of said addressable memory banks has been removed, the combination therewith of a memory expansion circuit comprising: (a) a plurality of expansion memory banks each having a plurality of expansion memory devices arranged in a row, said rows of expansion memory devices electrically connected in parallel to one another and one row of said expansion memory devices connected to said one multiple circuit connection from which said one addressable memory bank has been removed, each said expansion bank corresponding to each said addressable memory bank in said digital computer; (b) logic control means connected to said plurality of expansion memory banks and having first and second operating modes; (c) input/output means operationally connecting said multiple circuit connections of said one row of said addressable memory devices to said plurality of expansion memory banks and to said logic control means; (d) said logic control means responsive to said address and control signals to said one row of addressable memory deviced to operate in said first mode to select and make operational a particular one of said plurality of expansion memory banks; and (e) said logic control means operating in said second mode in the absence of said predetermined combination of signals to enable said data signals to be stored in and retrieved from said expansion memory bank selected by said digital decode means to be operational in said first operational mode, said digital decoder means including an N-bit latch for inserting and storing said predetermined combination of said data signals when said logic control means is in said first operating mode, and for retaining said predetermined combination of said data signals when said logic control means is in said second operating mode.

Claim 8

In a data processing unit according to claim 5, said logic control means operating in said second mode in the absence of said address and control signals to enable data signals to be stored in and retrieved from said selected expansion memory bank.

Claim 9

In a data processing unit according to claim 5, said input/output means having a digital decoder and a buffered input/output line connected to said data processing unit.

Claim 10

In the data processing unit of claim 5, wherein said memory expansion devices are dynamic random access memory devices.

Claim 11

In the data processing unit of claim 5, wherein each of said expansion memory banks is connected in parallel to said data processing unit via said one multiple circuit connection.

Claim 12

In the data processing unit of claim 5, said digital decoder comprises an N-bit latch for inserting and storing data signals when said logic control means is in said first operating mode, and for retaining said data signals when said logic control means is in said second operating mode.

Claim 13

In the data processing unit of claim 10, said digital decoder having an N-line-to-M-line logic decoder connected to said N-bit latch for decoding selected data signals and for producing a selection signal for selecting and making operational a selected one of said expansion memory banks.