EP0206486A2
Expired / Lapsed
EP
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Memory test circuit
Assignee: Toshiba Corp
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Filing: 1986-05-08
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Granted: —
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Expires: 2006-05-08
Abstract
Abstract A memory test circuit is described. The memory test circuit comprises means (12, 13) for simultaneously writing identical test data into several memory cells (14), means (13) for simultaneously reading the test data written into the memory cells, means (16) for obtaining a first logical operation of the test data read from the memory cells, means (17) for obtaining a second logical operation of the test data read from the memory cells, and means (18,19, SW1, SW2) for inspecting whether or not the memory cells into which the test data is written operate correctly is carried out on the basis of the first logical operation and second logical operation of the test data read from the memory cells.
Inventors
- 👤 Tohru C/O Patent Division Furuyama
- 👤 Takashi C/O Patent Division Ohsawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 10:48
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/26; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G01R31/28; G01R31/317; G01R31/3181; G11C29/26; G11C29/38
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
123 words
A memory test circuit comprising: means (12, 13) (112, 113) for simultaneously writing identical test data into several memory cells (14) (114); means (13) (113) for simultaneously reading said test data written into said memory cells; and means (16) (116) for obtaining a first logical operation of said test data read from said memory cells; characterised by means (17) (117) for obtaining a second logical operation of said test data read from said memory cells; and means (18, 19, SW1, SW2) (121, SW1, SW2, SW3) for inspecting whether or not said memory cells into which said test data is written operate correctly on the basis of said first logical operation and second logical operation of said test data read from said memory cells.
Claim 2
Dependent Claim
123 words
A memory test circuit comprising: means (12, 13) (112, 113) for simultaneously writing identical test data into several memory cells (14) (114); means (13) (113) for simultaneously reading said test data written into said memory cells; and means (16) (116) for obtaining a first logical operation of said test data read from said memory cells; characterised by means (17) (117) for obtaining a second logical operation of said test data read from said memory cells; and means (18, 19, SW1, SW2) (121, SW1, SW2, SW3) for inspecting whether or not said memory cells into which said test data is written operate correctly on the basis of said first logical operation and second logical operation of said test data read from said memory cells.
Claim 3
Dependent Claim
46 words
A memory test circuit according to claim 1, wherein said first logical operation is a logical product (16) of said test data read from said memory cells and said second logical operation is a logical sum (17) of said test data read from said memory cells.
Claim 4
Dependent Claim
67 words
A memory test circuit according to claim 2, wherein said memory test circuit further comprises means for obtaining an exclusive logical sum (18) of said logical product (16) and logical sum (17) of said test data and wherein an inspection of whether or not said memory cells into which said test data is written operate correctly is carried out on the basis of said exclusive logical sum.
Claim 5
Dependent Claim
56 words
A memory test circuit according to claim 2, wherein an inspection of whether or not said memory cells into which said test data is written operate correctly is carried out on the basis of a comparison of said test data with said logical product and logical sum of said test data read from said memory cells.
Claim 6
Dependent Claim
70 words
A memory test circuit according to claim 4, wherein said memory test circuit is further provided with control means for which selects as an output said logical product when said test data written is "1", and as an output said logical sum when said test data written is"0", when comparing said written test data with said logical product and logical sum of said test data read from said memory cells.
References Cited (Backward Citations)
No citation records indexed.
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