Reconfigurable contiguous address space memory system including serially connected variable capacity memory modules and a split address bus

Claim 2

A memory system providing a contiguous memory address space to a central processing unit connected to the memory system by an information bus for the transfer of address and data information, said memory system comprising: a plurality of removable memory modules connected in series to the information bus for sending and receiving data information and a first portion of address information, each module including means for providing module memory capacity and first decoder means for receiving a module select signal and for receiving said a first portion of address information and providing access to memory locations therein in response to said first portion of address information and the reception of said module select signal; and control means for receiving a start address from the central processing unit and connected to the information bus for receiving and sending data information and the remaining portion of address information from said central processing unit and connected to each memory module for receiving the memory module capacity from each memory module, said control means for allocating address ranges for each of the memory modules and for sending the module select signal to an individual one of said memory modules when the remaining portion of addressed information received is within the address range allocated for the individual one of said memory modules.

Claim 3

A memory system according to claim 1 wherein said control means includes adder means for adding the start address to the memory capacity of a memory module to compute the module address range and a next serially connected memory module start address.

Claim 4

A memory system according to claim 1 wherein said information bus includes a plurality of parallel address lines, including high to low ordered parallel bit lines, for the transfer of address information, the first portion of address information lines being a low ordered plurality of said address lines and the remaining portion of address information lines being a high ordered plurality of the remaining address lines.

Claim 5

A memory system for providing a contiguous memory address space, said memory system connected to a central processing unit by an information bus for the transfer of address and data information, said information bus including a data bus and an address bus having a high to low ordered plurality of parallel bit lines, said memory system comprising: a plurality of removable memory modules connected in series to the data bus and a low ordered portion of said addresss bus bit lines, each module including: (i) memory means for the storage of data according to a low ordered address; (ii) means for providing memory module storage capacity; (iii) low order address decode means for decoding a low order address from the low ordered portion of address bus bit lines upon the occurrence of a memory module select signal and for sending or receiving data on the data bus corresponding to the low ordered address on the address bus and in response thereto; and a memory controller remotely located from the memory modules and including a plurality of adder means connected in series and high order address decode means corresponding to an individual one of said memory modules, each adder means connected to receive from each memory module said memory capacity corresponding memory module and for receiving a memory module start address from the central processing unit or a next start address from a preceding serially located adder means and for computing an address range for the memory module and a next start address for the next serially connected memory module and adder means, the high order address decode means connected to its adder means to receive the memory module address range and connected to the high ordered portion of the address bus, said high order address decode means for receiving address data from the high ordered portion of the address bus and providing the memory module select signal when the address data is within the address range for its respective memory module.

Claim 6

A memory system for providing a contiguous memory address space, said memory system connected to a central processing unit by an information bus for the transfer of address and data information, said information bus including a data bus and an address bus having a high to low ordered plurality of parallel bit lines, said memory system comprising: a plurality of removable memory modules connected in series to the data bus and a low ordered portion of said addresss bus bit lines, each module including: (i) memory means for the storage of data according to a low ordered address; (ii) means for providing memory module storage capacity; (iii) low order address decode means for decoding a low order address from the low ordered portion of address bus bit lines upon the occurrence of a memory module select signal and for sending or receiving data on the data bus corresponding to the low ordered address on the address bus and in response thereto; and a memory controller remotely located from the memory modules and including a plurality of adder means connected in series and high order address decode means corresponding to an individual one of said memory modules, each adder means connected to receive from each memory module said memory capacity corresponding memory module and for receiving a memory module start address from the central processing unit or a next start address from a preceding serially located adder means and for computing an address range for the memory module and a next start address for the next serially connected memory module and adder means, the high order address decode means connected to its adder means to receive the memory module address range and connected to the high ordered portion of the address bus, said high order address decode means for receiving address data from the high ordered portion of the address bus and providing the memory module select signal when the address data is within the address range for its respective memory module.

Claim 7

A memory system according to claim 4 wherein the adder means for computing the next start address for the next serially connected memory and adder means includes means for computing this next start address to be contiguous with the highest address for the computed memory module range.

Claim 8

A memory system according to claim 5 wherein the low ordered portion of the address bus bit lines are connected to the means for providing the memory module storage capacity.

Claim 9

A memory system according to claim 6 wherein the information bus includes control lines for providing control signals from the central processing unit for controlling the direction of data flow over the low ordered portion of the address bus bit lines providing the low order address and the memory module storage capacity.