US4970689A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Charge amplifying trench memory cell
Assignee: International Business Machines Corp
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Filing: 1990-02-26
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Granted: 1990-11-13
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Expires: 2010-02-26
Abstract
Abstract A gain memory cell circuit includes a storage capacitor connected between a storage node and ground, a write word line, a read word line, a second capacitor capactively coupling the read word line to the storage node, a read transistor having its source/drain path coupled between the bit line and ground and having its gate coupled to the storage node, and a write transistor having its source/drain path coupled between the storage node and bit line and a control electrode connected to the write word line.
Inventors
- 👤 Donald M. Kenney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:48
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; Y; Y10; Y10S; Y10S257/00; Y10S257/905
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
193 words
A gain memory cell circuit, comprising: a first capacitor connected between a storage node and a first predetermined potential; a bit signal node for providing an input data signal and for outputting a stored data signal representing stored data; a write control node for providing a write control signal to transfer said input data signal from said bit signal node to said storage node; a read control node for providing a read control signal for generating said stored data signal on said bit signal node in accordance with the data stored on said storage node; a second capacitor connected between said storage node and said read control node; a read transistor having principal current electrodes connected to said bit signal node and to said predetermined potential and having a control electrode connected to said storage node for generating said stored data signal on said bit signal node in response to said read control signal and in accordance with said data stored on said storage node; and a write transistor having principal current electrodes connected to said storage node and said bit signal node and a control electrode connected to said write control node.
Claim 2
Dependent Claim
193 words
A gain memory cell circuit, comprising: a first capacitor connected between a storage node and a first predetermined potential; a bit signal node for providing an input data signal and for outputting a stored data signal representing stored data; a write control node for providing a write control signal to transfer said input data signal from said bit signal node to said storage node; a read control node for providing a read control signal for generating said stored data signal on said bit signal node in accordance with the data stored on said storage node; a second capacitor connected between said storage node and said read control node; a read transistor having principal current electrodes connected to said bit signal node and to said predetermined potential and having a control electrode connected to said storage node for generating said stored data signal on said bit signal node in response to said read control signal and in accordance with said data stored on said storage node; and a write transistor having principal current electrodes connected to said storage node and said bit signal node and a control electrode connected to said write control node.
Claim 3
Dependent Claim
38 words
A gain memory cell circuit as recited in claim 1, further comprising an isolation transistor having principal current electrodes connected to said predetermined potential and said storage node and having a control electrode connected to said storage node.
Claim 4
Dependent Claim
40 words
A gain memory cell circuit as recited in claim 2, wherein said read, write and isolation transistors are MOS transistors and wherein said write transistor has a voltage threshold of lesser magnitude than those for said read and isolation transistors.
Claim 5
Dependent Claim
18 words
A gain memory cell circuit as recited in claim 3, wherein said MOS transistors are all of p-type.
Claim 6
Dependent Claim
23 words
A gain memory cell circuit as recited in claim 4, wherein all of said transistors and capacitors are formed in an integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-12 | 1994-05-14 | 1994-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-12 | 1998-05-14 | 1998-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-12 | 2002-05-14 | 2002-11-13 | $7700.00 | Window Closed / Lapsed |