Reference voltage generator for precharging bit lines of a transistor memory

Claim 2

In a solid state memory device, a threshold generator for generating a reference potential for precharging bit lines of said memory comprising: a first inverter circuit having a threshold voltage below said reference potential; a second inverter circuit having a threshold voltage above said reference voltage, said first and second inverters having a common input connection; voltage drive means to supply a current from a voltage source VDD, in response to an output signal of said first inverter circuit, and for discharging a current from said bit line in response to an output signal of said second inverter circuit; and, a bit line driving connection connecting said voltage drive means and inverter circuit common input connection, said inverter circuits supplying a charging current and discharging current to and from said bit line to maintain a voltage on said bit line driving connection within a range defined by said threshold voltages.

Claim 3

The threshold generator of claim 1 wherein each of said inverter circuits comprises a P channel FET connected in series with an N channel FET, said P channel and N channel FETs having a common gate connection.

Claim 4

The threshold generator of claim 1 wherein said first inverter circuit threshold is substantially 2 volts.

Claim 5

The threshold generator of claim 2 wherein said voltage drive means comprises: first and second serially connected P channel and N channel FET transistors, forming an output terminal, said serially connected transistors being adapted to be connected between terminals of a voltage supply VDD; and third and fourth inverter circuits connecting gate connections of said P channel and N channel FET transistors to output terminals of said first and second inverter circuits.

Claim 6

In a solid state memory device, a bit line driving circuit for precharging bit lines at one half VDD voltage levels comprising: a first inverter circuit having a threshold voltage which lies within the voltage range 0 to VDD; a second inverter circuit having a threshold voltage greater than said first inverter threshold and less than VDD, said first and second inverter circuits having a common input connection; first and second serially connected MOS transistors connected between first and second terminals of a voltage source of VDD volts, each having a gate connection; third and fourth inverter circuits connecting respective outputs of said first and second inverters to gate connections of said first and second serially connected MOS transistors; and, a feedback path connecting a junction formed by said first and second serially connected MOS transistors to said common input connection, whereby said common input connection is maintained at a voltage potential between said first and second inverter threshold voltages.

Claim 7

In a solid state memory device, a bit line driving circuit for precharging bit lines at one half VDD voltage levels comprising: a first inverter circuit having a threshold voltage which lies within the voltage range 0 to VDD; a second inverter circuit having a threshold voltage greater than said first inverter threshold and less than VDD, said first and second inverter circuits having a common input connection; first and second serially connected MOS transistors connected between first and second terminals of a voltage source of VDD volts, each having a gate connection; third and fourth inverter circuits connecting respective outputs of said first and second inverters to gate connections of said first and second serially connected MOS transistors; and, a feedback path connecting a junction formed by said first and second serially connected MOS transistors to said common input connection, whereby said common input connection is maintained at a voltage potential between said first and second inverter threshold voltages.

Claim 8

The threshold generator of claim 5 wherein said first and second inverters each comprise a series connected P channel FET and N channel FET having a common gate connection forming an input, each having a channel width/length ratio selected to provide a respective inverter threshold voltage.