US4633442A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Protective circuitry for a read only memory
Assignee: Raytheon Co
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Filing: 1985-02-04
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Granted: 1986-12-30
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Expires: 2005-02-04
Abstract
Abstract Protective circuitry for a monolithic ROM is shown to include six monolithic FETS interconnected so that two comprise a resistance-capacitance series circuit responsive to a biasing voltage applied thereto to produce a time-varying voltage and the remaining four monolithic FETS are interconnected to form a latching circuit having a "high" output when the time-varying voltage is below a predetermined level and a "low" output thereafter as long as the biasing voltage is applied.
Inventors
- 👤 Michael N. Borghese
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:01
CPC Classifications
G; G11; G11C; G11C17/00; G11C5/00; G11C5/14; G11C5/143
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
319 words
In combination with a monolithic read only memory wherein, on start-up, elements must be biased before extant address signals are effective, the improvement comprising: (a) precharge circuitry connected to the output bit lines of the read only memory; and (b) actuating means for the precharge circuitry including monolithic circuitry for producing, when a biasing voltage is first applied and for a predetermined interval thereafter, a first signal at a logic zero level, means for inverting the first signal to a second signal at a logic one level, and logic circuits responsive to the second signal and to the extant address signals to control the precharge circuitry wherein the monolithic circuitry comprises: (i) a first p-channel and a first n-channel field effect transistor, each having a gate, drain and source electrode, the gate and drain electrodes of the first p-channel field effect transistor being connected so that that transistor may simulate a resistor and the source and drain electrodes of the first n-channel field effect transistor may simulate a capacitor; (ii) means connecting the biasing voltage to the drain electrode of the first p-channel field effect transistor, the gate and source electrodes of the first p-channel field effect transistor to the gate electrode of the first n-channel field effect transistor and the drain and the source electrodes of the first n-channel transistor to ground to produce, when the biasing voltage is first applied, a time-varying voltage at the gate electrode of the first n-channel field effect transistor, said time-varying voltage changing exponentially from ground potential to a voltage approximating the bias voltage; and (iii) level conversion means, responsive to the level of the time-varying voltage, to produce a voltage essentially at the bias voltage as long as the time-varying voltage is below a predetermined level intermediate ground potential and the biasing voltage and thereafter, as long as the biasing voltage is applied, a voltage at a level approximating ground potential.
Claim 2
Dependent Claim
319 words
In combination with a monolithic read only memory wherein, on start-up, elements must be biased before extant address signals are effective, the improvement comprising: (a) precharge circuitry connected to the output bit lines of the read only memory; and (b) actuating means for the precharge circuitry including monolithic circuitry for producing, when a biasing voltage is first applied and for a predetermined interval thereafter, a first signal at a logic zero level, means for inverting the first signal to a second signal at a logic one level, and logic circuits responsive to the second signal and to the extant address signals to control the precharge circuitry wherein the monolithic circuitry comprises: (i) a first p-channel and a first n-channel field effect transistor, each having a gate, drain and source electrode, the gate and drain electrodes of the first p-channel field effect transistor being connected so that that transistor may simulate a resistor and the source and drain electrodes of the first n-channel field effect transistor may simulate a capacitor; (ii) means connecting the biasing voltage to the drain electrode of the first p-channel field effect transistor, the gate and source electrodes of the first p-channel field effect transistor to the gate electrode of the first n-channel field effect transistor and the drain and the source electrodes of the first n-channel transistor to ground to produce, when the biasing voltage is first applied, a time-varying voltage at the gate electrode of the first n-channel field effect transistor, said time-varying voltage changing exponentially from ground potential to a voltage approximating the bias voltage; and (iii) level conversion means, responsive to the level of the time-varying voltage, to produce a voltage essentially at the bias voltage as long as the time-varying voltage is below a predetermined level intermediate ground potential and the biasing voltage and thereafter, as long as the biasing voltage is applied, a voltage at a level approximating ground potential.
Claim 3
Dependent Claim
261 words
The improvement as in claim 1 wherein the level conversion means is formed by monolithic circuitry comprising: (a) a second and a third p-channel field effect transistor and a second and a third n-channel field effect transistor, each one of said transistors having a gate, drain and source electrode; (b) means for connecting the drain electrodes of the second and the third p-channel field effect transistors to the biasing voltage and the source electrodes of the second and third p-channel field effect transistors to the drain electrodes of the second and third n-channel field effect transistors and the source electrodes of the second and third n-channel field effect transistors to ground potential; (c) means for connecting the gate electrodes of the second p-channel and the second n-channel field effect transistors to the gate electrode of the first n-channel field effect transistor; (d) means for connecting the gate electrode of the third p-chanel field effect transistor to ground potential; (e) means for interconnecting the source electrode of the second p-channel field effect transistor, the drain electrode of the second n-channel field effect transistor and the gate electrode of the third n-channel field effect transistor; (f) means for connecting the source electrode of the third p-channel field effect transistor and the drain electrode of the third n-channel field effect transistor; and (g) means for connecting the source electrode of the third p-channel field effect transistor to the switching means to actuate the switching means in accordance with the level of the voltage at the source electrode of the third p-channel field effect transistor.
References Cited (Backward Citations)
US4417328A
Cited
US4558435A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |