Page interleaved memory access

Claim 1

A high-performance memory controller for a memory that is divided into banks, said memory being arranged in a plurality of rows and a plurality of columns, each row and column being individually addressed, each row requiring a pre-charge cycle prior to being accessed, comprising in combination: a memory addressing bus that has at least one page indicating bit which indicates if a particular address is on an odd or an even page of said memory, said odd and even pages being in different ones of said banks, each page being one of said rows of memory; means, coupled to said memory addressing bus, for switching between rows of said memory, in response to the value of said page addressing bit, by enabling an appropriate one of said banks; means, coupled to said memory addressing bus, for registering the last row that was accessed in each bank of said memory from the row address bits of a last memory address, said row address bits being more significant than said page addressing bit; means for comparing the row address of a current address to said row address in said means for registering and providing a row pre-charge cycle to a bank of said memory enabled by said switching means only when said current and last row address are different; and whereby sequential memory accesses to the same row in said memory are started without waiting for a row pre-charge cycle to be completed.