Power transistor with integrated gate resistor

Claim 1

A vertical DMOS power transistor with an integrated gate resistor comprising: a semiconductor substrate having a first region of a first conductivity type and a second region of a second, opposite conductivity type generally surrounding the first region and forming a junction with the first region; an insulting layer on the substrate over the first region and at least a portion of the second region; a doped polycrystalline silicon layer on the insulating layer a portion of which acts as a gate; a first conductive gate element on the polycrystalline silicon layer and positioned generally over the first region; a second conductive gate element on the polycrystalline silicon layer and spaced from and generally surrounding the first conductive gate element; a drain contact on the substrate and spaced apart from the insulating layer; and the portion of the polycrystalline silicon layer connecting the first and second conductive gate elements being a resistor element having a plurality of openings provided therethrough, the polycrystalline silicon layer thereby including a plurality of resistor regions, each of said resistor regions being connected to said first conductive gate element and said second conductive gate element, and whereby a resistance of said resistor element is a function of the sizes of said openings.