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US4451328A Expired / Lapsed US ⏱️ 0.0 years remaining

Manufacturing TaSi-polysilicon conductors having high-resistance elements by a liftoff technique

Assignee: SOCITE POUR L'ETUDE ET LA FABRICATION DE CIRCUITS INTEGRES SPECIAUX-EFCIS 17
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Filing: 1982-09-27
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Granted: 1984-05-29
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Expires: 2002-09-27
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Abstract

Abstract A process for manufacturing high-resistance elements for integrated circuits, in which the resistors are positioned on a layer of silica covering an integrated circuit, in a polycrystalline silicon zone possessing high resistivity, current supply lines being formed of a layer of polycrystalline silicon possessing low resistivity, surmounted by a layer of tantalum silicide. Plugs of photosensitive resin, deposited on a layer of polycrystalline silicon, are used to mark out a zone where the resistor is to be positioned, from zones in which resistivity is reduced by doping, and also to "lift-off" the layer of tantalum silicide on top of the resistor position.

Inventors

  • 👤 Guy Dubois

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 19:52
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10P; H10P76/00; H10P76/20; H10P76/202

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 174 words
A process for manufacturing high-resistance elements as part of an integrated circuit production procedure, in which access lines to certain elementary transistor terminals are formed of conducting strips, obtained by superimposing a strip of strongly doped polycrystalline silicon and a strip of metal silicide, such resistors being positioned at places where the integrated circuit surface is coated with a thick layer of oxide, said process comprising the following steps: depositing on an oxide coated integrated circuit surface a layer of polycrystalline silicon possessing high resistivity; depositing on said polycrystalline silicon layer at places where resistors are required plugs of photosensitive substance; doping the polycrystalline silicon to endow it with low resistivity except at places protected by said photosensitive substance; depositing a silicide over the entire surface of the integrated circuit including the unmasked polycrystalline silicon and the plugs; removing by chemical lift-off the photosensitive plugs and portions of silicide covering them; selectively masking and etching said silicide and polycrystalline silicon to form said lines, some at least of which pass over the plug positions.
Claim 2
Dependent Claim 174 words
A process for manufacturing high-resistance elements as part of an integrated circuit production procedure, in which access lines to certain elementary transistor terminals are formed of conducting strips, obtained by superimposing a strip of strongly doped polycrystalline silicon and a strip of metal silicide, such resistors being positioned at places where the integrated circuit surface is coated with a thick layer of oxide, said process comprising the following steps: depositing on an oxide coated integrated circuit surface a layer of polycrystalline silicon possessing high resistivity; depositing on said polycrystalline silicon layer at places where resistors are required plugs of photosensitive substance; doping the polycrystalline silicon to endow it with low resistivity except at places protected by said photosensitive substance; depositing a silicide over the entire surface of the integrated circuit including the unmasked polycrystalline silicon and the plugs; removing by chemical lift-off the photosensitive plugs and portions of silicide covering them; selectively masking and etching said silicide and polycrystalline silicon to form said lines, some at least of which pass over the plug positions.
Claim 3
Dependent Claim 15 words
A process as defined in claim 1, in which the metal silicide is tantalum silicide.
Claim 4
Dependent Claim 20 words
A process as defined in claim 1, in which said step of masking and etching precedes said step of removing.

References Cited (Backward Citations)

FR2269199A1 Cited
US4214917A Cited
US4297721A Cited
US4332839A Cited
US4267558A Cited
US4265685A Cited
US4291328A Cited
US4362597A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-05-29 1987-11-28 1988-05-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-05-29 1991-11-28 1992-05-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-05-29 1995-11-28 1996-05-29 $7700.00 Window Closed / Lapsed

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