US4602170A
Expired / Lapsed
US
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Resistive gate field effect transistor logic family
Assignee: International Business Machines Corp
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Filing: 1983-09-08
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Granted: 1986-07-22
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Expires: 2003-09-08
Abstract
Abstract A family of digital logic circuits constructed with resistive gate field effect transistors is provided. The logic circuits are comprised of AND and OR circuits, each implemented with resistive gate devices. In constructing the AND circuit, the resistive gate lies along the length of the channel region between the source and drain of the device. Logic input signals are selectively applied along the length of the channel region to the resistive gate. The device will conduct between source and drain only if all points along the channel are above the local threshold voltage of the channel region which will occur when appropriate logic signals are applied simultaneously to all logic input terminals. A logic OR device is realized when the resistive gate is formed transverse to the channel such that each input to the gate controls a portion of the channel between the source and drain. NAND and NOR circuits are provided using the resistive gate logic device in an inverter circuit.
Inventors
- 👤 Claude L. Bertin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:56
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/605; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
78 words
A field effect transistor logic circuit comprising: a resistive gate field effect transistor device having a gate electrode composed of a resistive material and at least two input electrodes attached to different portions of the resistive gate, each input electrode being responsive to an independent logic level input signal to independently control the conductivity of different portions of the field effect transistor device channel region as a function of the logic states of the logic level input signals.
Claim 2
Dependent Claim
78 words
A field effect transistor logic circuit comprising: a resistive gate field effect transistor device having a gate electrode composed of a resistive material and at least two input electrodes attached to different portions of the resistive gate, each input electrode being responsive to an independent logic level input signal to independently control the conductivity of different portions of the field effect transistor device channel region as a function of the logic states of the logic level input signals.
Claim 3
Dependent Claim
78 words
The field effect transistor logic circuit as claimed in claim 1, wherein said resistive gate field effect transistor device has a source region, a drain region and a channel region therebetween, said gate electrode extending across the length of said channel region between said source and drain region, the resistivity of said gate electrode being selected such that the channel region will conduct only in the presence of at least two independent logic level input signals simultaneously received.
Claim 4
Dependent Claim
81 words
The field effect transistor logic circuit as claimed in claim 1, wherein said resistive gate field effect transistor device has a source region, a drain region and a channel region, said gate electrode extending across the width of said channel region, the resistivity of said gate electrode being selected such that the channel region will conduct between the source and drain in response to a single logic level input signal applied to any one of said at least two input electrodes.
Claim 5
Dependent Claim
22 words
The field effect transistor logic circuit as claimed in claim 1, wherein said resistive material for said gate electrode is polycrystalline silicon.
Claim 6
Dependent Claim
118 words
A field effect transistor AND type logic circuit comprising: a resistive gate field effect transistor device having a source region, a drain region, a channel region and a gate electrode composed of a resistive material situated over said channel region between said source and drain, at least first and second input terminals connected to different portions of said resistive gate and responsive to independent logic level signals, different portions of said channel being responsive to logic level signals applied to different ones of said input terminals such that each logic level input signal causes only a portion of the channel to conduct, but is insufficient to cause conduction across the entire channel length between the source and drain.
Claim 7
Dependent Claim
118 words
A field effect transistor AND type logic circuit comprising: a resistive gate field effect transistor device having a source region, a drain region, a channel region and a gate electrode composed of a resistive material situated over said channel region between said source and drain, at least first and second input terminals connected to different portions of said resistive gate and responsive to independent logic level signals, different portions of said channel being responsive to logic level signals applied to different ones of said input terminals such that each logic level input signal causes only a portion of the channel to conduct, but is insufficient to cause conduction across the entire channel length between the source and drain.
Claim 8
Dependent Claim
107 words
A field effect transistor OR type logic circuit comprising: a resistive gate field effect transistor device having a source region, a drain region, a channel region and a gate electrode composed of a resistive material extending along the width of said channel, at least first and second input terminals connected to different portions of said resistive gate and responsive to independent logic level signals, different portions of said channel along its width being responsive to logic level signals applied to different ones of said input terminals such that each logic level input signal causes a portion of the channel to conduct between the source and drain regions.
Claim 9
Dependent Claim
107 words
A field effect transistor OR type logic circuit comprising: a resistive gate field effect transistor device having a source region, a drain region, a channel region and a gate electrode composed of a resistive material extending along the width of said channel, at least first and second input terminals connected to different portions of said resistive gate and responsive to independent logic level signals, different portions of said channel along its width being responsive to logic level signals applied to different ones of said input terminals such that each logic level input signal causes a portion of the channel to conduct between the source and drain regions.
Claim 10
Dependent Claim
192 words
A field effect transistor logic circuit comprising: first and second resistive gate field effect transistor devices; each of said resistive gate field effect transistor devices having a source region, a drain region, a channel region, gate electrode composed of a resistive material situated over said channel region between said source and drain regions and at least first and second input terminals connected to different portions of said resistive gate, each of said input terminals being responsive to independent logic level signals, different portions of said channel being responsive to logic level signals applied to different ones of said input terminals such that each logic level input signal causes only a portion of the channel to conduct, conduction between source and drain occurring only in the presence of logic level input signals to all the input terminals simultaneously; the drain of said first resistive gate field effect transistor being connected to the drain of said second resistive gate field effect transistor, the source of said first resistive gate field effect transistor being connected to the source of said second resistive gate field effect transistor; and a load resistance connected to said interconnected drains.
Claim 11
Dependent Claim
192 words
A field effect transistor logic circuit comprising: first and second resistive gate field effect transistor devices; each of said resistive gate field effect transistor devices having a source region, a drain region, a channel region, gate electrode composed of a resistive material situated over said channel region between said source and drain regions and at least first and second input terminals connected to different portions of said resistive gate, each of said input terminals being responsive to independent logic level signals, different portions of said channel being responsive to logic level signals applied to different ones of said input terminals such that each logic level input signal causes only a portion of the channel to conduct, conduction between source and drain occurring only in the presence of logic level input signals to all the input terminals simultaneously; the drain of said first resistive gate field effect transistor being connected to the drain of said second resistive gate field effect transistor, the source of said first resistive gate field effect transistor being connected to the source of said second resistive gate field effect transistor; and a load resistance connected to said interconnected drains.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-21 | 1990-01-20 | 1990-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-21 | 1994-01-20 | 1994-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-21 | 1998-01-20 | 1998-07-22 | $7700.00 | Window Closed / Lapsed |