US4074151A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS interchip receiver differential amplifiers employing CMOS amplifiers having parallel connected CMOS transistors as feedback shunt impedance paths
Assignee: International Business Machines Corp
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Filing: 1976-06-30
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Granted: 1978-02-14
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Expires: 1996-06-30
Abstract
Abstract A negative shunt feedback CMOS amplifier is disclosed for connection to the output nodes of MOS interchip digital signal receiver differential amplifiers which have highly capacitive output nodes in order to bypass the large capacitance to thereby extract a high speed current signal. A first embodiment of the invention uses a resistor as the shunt feedback and a second embodiment of the invention, to which this application is directed to, uses parallel N-channel and P-channel FETs to form the shunt feedback impedance.
Inventors
- 👤 Frederick Buckley, III
- 👤 Gerald A. Miller
- 👤 Vincent A. Scotto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:16
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; H03K19/00; H03K19/01; H03K19/017; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
226 words
A high performance digital signal receiver circuit, comprising: an FET differential amplifier having a first input connected to an input signal source, a second input connected to a reference voltage, and a differential amplifier output node characterized by a large source capacitance; a negative feedback amplifier in shunt feedback configuration having its input terminal connected to said differential amplifier output node for providing a low impedance path for current around said capacitance and whose output constitutes the output terminal for said receiver circuit; said feedback amplifier further comprising: a first P-channel FET device having a source connected to a relatively high supply voltage and a drain connected to said amplifier output terminal and to the drain of a first n-channel FET device having its source connected to a relatively low supply voltage; said first P-channel FET device having a gate electrode connected to said amplifier input terminal and said first N-channel FET device having a gate electrode connected to said amplifier input terminal; a second N-channel FET device and a second P-channel FET device mutually connected in parallel between said amplifier input and output terminals, with the gate of said second N-channel FET device connected to said relatively high supply voltage and the gate of said second P-channel FET device connected to said relatively low supply voltage; whereby a high speed digital signal receiver is formed.
Claim 2
Dependent Claim
226 words
A high performance digital signal receiver circuit, comprising: an FET differential amplifier having a first input connected to an input signal source, a second input connected to a reference voltage, and a differential amplifier output node characterized by a large source capacitance; a negative feedback amplifier in shunt feedback configuration having its input terminal connected to said differential amplifier output node for providing a low impedance path for current around said capacitance and whose output constitutes the output terminal for said receiver circuit; said feedback amplifier further comprising: a first P-channel FET device having a source connected to a relatively high supply voltage and a drain connected to said amplifier output terminal and to the drain of a first n-channel FET device having its source connected to a relatively low supply voltage; said first P-channel FET device having a gate electrode connected to said amplifier input terminal and said first N-channel FET device having a gate electrode connected to said amplifier input terminal; a second N-channel FET device and a second P-channel FET device mutually connected in parallel between said amplifier input and output terminals, with the gate of said second N-channel FET device connected to said relatively high supply voltage and the gate of said second P-channel FET device connected to said relatively low supply voltage; whereby a high speed digital signal receiver is formed.
Claim 3
Dependent Claim
145 words
The high performance digital signal receiver circuit of claim 1 wherein said FET differential amplifier further comprises: a first current source connected between a first supply voltage and a first node; a first N-channel FET device having its drain connected to said first node, its gate connected to said signal source and its source connected to a second node; a second current source connected between said second node and a second supply voltage; a third current source connected between said first supply voltage and a third node; a second N-channel FET device having its drain connected to said third node, its gate connected to said reference voltage and its source connected to said second node; said first node constituting said differential amplifier output node from which the true form of the signal from said signal source is generated and transmitted to said negative feedback amplifier.
Claim 4
Dependent Claim
55 words
The high performance digital signal receiver circuit of claim 2, which further comprises: a second negative feedback amplifier in shunt feedback configuration having its input terminal connected to said third node of said FET differential amplifier, for amplifying the complement form of the signal from said signal source which is generated at said third node.
Claim 5
Dependent Claim
171 words
The high performance digital signal receiver circuit of claim 1, wherein said FET differential amplifier further comprises: a first P-channel FET device having a source connected to a first supply voltage, and its gate and drain connected to a first node; a first N-channel FET device having its drain connected to said first node, its gate connected to said signal source, and its source connected to a second node; a second N-channel FET device having its drain connected to said second node, its gate connected to a second supply voltage, and its source connected to a third supply voltage; a second P-channel FET device having its source connected to said first supply voltage, its gate connected to said first node, and its drain connected to a third node; a third N-channel FET device having its drain connected to said third node, its gate connected to said reference voltage, and its source connected to said second node; said third node constituting said differential amplifier output node connected to said negative feedback amplifier.
Claim 6
Dependent Claim
221 words
The high performance digital signal receiver circuit of claim 1, wherein said FET differential amplifier further comprises: a first P-channel FET device having a source connected to a first supply voltage, a gate connected to a second supply voltage and a drain connected to a first node; a second P-channel FET device having a source connected to said first node, a gate connected to said input signal source, and a drain connected to a second node; a first N-channel FET device having a drain connected to said second node, a gate connected to said input signal source, and a source connected to a third node; a second N-channel FET device having a drain connected to said third node, a gate connected to a third supply voltage, and a source connected to a fourth supply voltage; a third P-channel FET device having a source connected to said first node, a gate connected to said reference voltage, and a drain connected to a fourth node; a third N-channel FET device having a drain connected to said fourth node, a gate connected to said reference voltage, and a source connected to said third node; said second node serving as said differential amplifier output node for generating and transmitting the true form of the signal from said input signal source to said negative feedback amplifier.
Claim 7
Dependent Claim
48 words
The high performance digital signal receiver circuit of claim 5, which further comprises: a second negative feedback amplifier in shunt feedback configuration having its input terminal connected to said fourth node of said differential amplifier, for amplifying the complement form of said signal from siad input signal source.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-13 | 1981-08-15 | 1982-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-13 | 1985-08-15 | 1986-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-13 | 1989-08-15 | 1990-02-14 | $7700.00 | Window Closed / Lapsed |