MOSFET comparator

Claim 2

A comparator comprising: a. a source of potential having at least a first and a second voltage level and said first level being more negative than said second level; b. a MOSFET biasing network connected between said first and second level of potential for providing a reference voltage; c. a MOSFET differential amplifier having a MOSFET constant current source responsive to said reference voltage from said biasing network for providing a constant current, and a MOSFET input stage being connected in series with said constant current source and having a first input terminal and a second input terminal for receiving two input signals to be compared and a MOSFET load network connected in series with said input stage, and an output terminal for providing a single differential output signal; and d. an output stage responsive to said single differential output signal for providing an amplified output signal, wherein said output stage includes: e. an N-channel MOSFET device having source, drain and gate electrodes; f. a first P-channel MOSFET device having source, drain and gate electrodes; g. a second P-channel MOSFET device having source, drain and gate electrodes; h. said source electrode of said N-channel device being connected to said first voltage level; i. said gate electrode of said N-channel device being connected to said gate electrode of said first P-channel device and said gate electrode of ssid N-channel device being further connected to said output terminal of said differential amplifier; j. said drain electrode of said N-channel device being connected to said drain electrode of said first P-channel device; k. said source electrode of said first P-channel device being connected to said drain electrode and said gate electrode of said second P-channel MOSFET device; l. said source electrode of said second P-channel device being connected to said second voltage level; and m. said junction of said drain electrode of said N-channel device and said drain electrode of said first P-channel device furnishing an output signal.

Claim 3

A comparator comprising: a. a source of potential having at least a first and a second voltage level and said first level being more negative than said second level; b. a MOSFET biasing network connected between said first and second level of potential for providing a reference voltage; c. a MOSFET differential amplifier having a MOSFET constant current source responsive to said reference voltage from said biasing network for providing a constant current, and a MOSFET input stage being connected in series with said constant current source and having a first input terminal and a second input terminal for receiving two input signals to be compared and a MOSFET load network connected in series with said input stage, and an output terminal for providing a single differential output signal; and d. an output stage responsive to said single differential output signal for providing an amplified output signal, wherein said input stage comprises: e. a first P-channel device having source, drain and gate electrodes; f. a second P-channel device having source, drain and gate electrodes; g. said source electrodes of said first and second P-channel device being connected together and being connected to said constant current source; h. said gate electrode of said first P-channel device being adapted to receive a first input signal to be compared; and i. said gate electrode of said second P-channel device being adapted to receive a second input signal to be compared wherein said load network comprises: j. a first N-channel device having source, drain and gate electrodes; k. a second N-channel device having source, drain and gate electrodes; l. said drain electrode of said first N-channel device being connected to said gate electrode of said first N-channel device and said gate electrode of said second N-channel device; m. said source electrode of said first N-channel device being connected to said source electrode of said second N-channel device and to said first voltage level; n. said drain electrode of said first N-channel device being connected to said drain electrode of said first P-channel device in said input stage; and o. said drain electrode of said second N-channel device being connected to said drain electrode of said second P-channel device in said input stage forming an output terminal.

Claim 4

A comparator comprising: a. a source of potential having at least a first and a second voltage level and said first level being more negative than said second level; b. a MOSFET biasing network connected between said first and second level of potential for providing a reference voltage; c. a MOSFET differential amplifier having a MOSFET constant current source responsive to said reference voltage from said biasing network for providing a constant current, and a MOSFET input stage being connected in series with said constant current source and having a first input terminal and a second input terminal for receiving two input signals to be compared and a MOSFET load network connected in series with said input stage, and an output terminal for providing a single differential output signal; and d. an output stage responsive to said single differential output signal for providing an amplified output signal, wherein said input stage comprises: e. a first P-channel device having source, drain and gate electrodes; f. a second P-channel device having source, drain and gate electrodes; g. said source electrodes of said first and second P-channel device being connected together and being connected to said constant current source; h. said gate electrode of said first P-channel device being adapted to receive a first input signal to be compared; and i. said gate electrode of said second P-channel device being adapted to receive a second input signal to be compared wherein said load network comprises: j. a first N-channel device having source, drain and gate electrodes; k. a second N-channel device having source, drain and gate electrodes; l. said drain electrode of said first N-channel device being connected to said gate electrode of said first N-channel device and said gate electrode of said second N-channel device; m. said source electrode of said first N-channel device being connected to said source electrode of said second N-channel device and to said first voltage level; n. said drain electrode of said first N-channel device being connected to said drain electrode of said first P-channel device in said input stage; and o. said drain electrode of said second N-channel device being connected to said drain electrode of said second P-channel device in said input stage forming an output terminal.

Claim 5

A comparator as received in claim 2, wherein said load stage further comprises: a. a first resistor being connected in series between said gate electrode of said first N-channel device in said load network and said drain electrode of said same device; b. a first output signal being available at the junction of said first resistor and said drain electrode of said first N-channel device; and c. a second resistor being connected in series between said gate electrode of said second N-channel device in said load network and said drain electrode of said same device.

Claim 6

A comparator comprising: a. source of potential having at least a first and a second voltage level and said first level being more negative than said second level; b. a MOSFET biasing network connected between said first level and said second level of potential for providing a reference voltage; c. a MOSFET differential amplifier having a MOSFET constant current source responsive to said reference voltage from said biasing network for providing a constant current, and a MOSFET input stage being connected in series with said constant current source and having a first input terminal and a second input terminal for receiving two signals to be compared and a MOSFET load network connected in series with said input stage, and output means for providing a single differential output signal; d. amplifing means responsive to said output signal for providing an amplified output signal; and e. voltage shifting means positioned in said bias networks and in said differential amplifier and in said output stage for providing a balanced output signal from said amplifying means, wherein said biasing network includes: f. an N-channel MOSFET device biasing source, drain and gate electrodes; g. a first P-channel MOSFET device having source, drain and gate electrodes; h. a second P-channel MOSFET device having source, drain and gate electrodes; i. said source electrode of said N-channel device being connected said first voltage level; j. said gate electrode of said N-channel device forming a junction with said drain electrode of said same device and that junction being connected to said drain electrode of said first P-channel device; k. said gate electrode of said first P-channel device being adapted to receive an input offset and bias adjust signal; said source electrode of said first P-channel device being connected to the junction of said gate electrode and said drain electrode of said second P-channel device; m. said source electrode of said second P-channel device being connected to said second voltage level; and n. said junction of said gate electrode and drain electrode of said second P-channel device furnishing a reference current, and wherein said output stage includes: o. an N-channel MOSFET device having source, drain and gate electrodes; p. a first P-channel MOSFET device having source, drain and gate electrodes; q. a second P-channel MOSFET device having source, drain and gate electrodes; r. said source electrode of said N-channel device being connected to said first voltage level; s. said gate electrode of said N-channel device being connected to said gate electrode of said first P-channel device and said gate electrode of said N-channel device being further connected to said output terminal of said differential amplifier; t. said drain electrode of said N-channel device being connected to said drain electrode of said first P-channel device; u. said source electrode of said first P-channel device being connected to said drain electrode and said gate electrode of said second P-channel MOSFET device; v. said source electrode of said second P-channel device being connected to said second voltage level; and w. said junction of said drain electrode of said N-channel device and said drain electrode of said first P-channel device furnishing an output signal.

Claim 7

A comparator comprising: a. source of potential having at least a first and a second voltage level and said first level being more negative than said second level; b. a MOSFET biasing network connected between said first level and said second level of potential for providing a reference voltage; c. a MOSFET differential amplifier having a MOSFET constant current source responsive to said reference voltage from said biasing network for providing a constant current, and a MOSFET input stage being connected in series with said constant current source and having a first input terminal and a second input terminal for receiving two signals to be compared and a MOSFET load network connected in series with said input stage, and output means for providing a single differential output signal; d. amplifing means responsive to said output signal for providing an amplified output signal; and e. voltage shifting means positioned in said bias networks and in said differential amplifier and in said output stage for providing a balanced output signal from said amplifying means, wherein said biasing network includes: f. an N-channel MOSFET device biasing source, drain and gate electrodes; g. a first P-channel MOSFET device having source, drain and gate electrodes; h. a second P-channel MOSFET device having source, drain and gate electrodes; i. said source electrode of said N-channel device being connected said first voltage level; j. said gate electrode of said N-channel device forming a junction with said drain electrode of said same device and that junction being connected to said drain electrode of said first P-channel device; k. said gate electrode of said first P-channel device being adapted to receive an input offset and bias adjust signal; said source electrode of said first P-channel device being connected to the junction of said gate electrode and said drain electrode of said second P-channel device; m. said source electrode of said second P-channel device being connected to said second voltage level; and n. said junction of said gate electrode and drain electrode of said second P-channel device furnishing a reference current, and wherein said output stage includes: o. an N-channel MOSFET device having source, drain and gate electrodes; p. a first P-channel MOSFET device having source, drain and gate electrodes; q. a second P-channel MOSFET device having source, drain and gate electrodes; r. said source electrode of said N-channel device being connected to said first voltage level; s. said gate electrode of said N-channel device being connected to said gate electrode of said first P-channel device and said gate electrode of said N-channel device being further connected to said output terminal of said differential amplifier; t. said drain electrode of said N-channel device being connected to said drain electrode of said first P-channel device; u. said source electrode of said first P-channel device being connected to said drain electrode and said gate electrode of said second P-channel MOSFET device; v. said source electrode of said second P-channel device being connected to said second voltage level; and w. said junction of said drain electrode of said N-channel device and said drain electrode of said first P-channel device furnishing an output signal.

Claim 8

A comparator as recited in claim 4, wherein said input stage comprises: a. a first P-channel device having source, drain and gate electrodes; b. a second P-channel device having source, drain and gate electrodes; c. said source electrodes of said first and second P-channel devices being connected together and being connected to said constant current source; d. said gate electrode of said first P-channel device being adapted to receive a first input signal to be compared; and e. said gate electrode of said second P-channel device being adapted to receive a second input signal to be compared.

Claim 9

A comparator as recited in claim 5, wherein said load network comprises: a. a first N-channel device having source, drain and gate electrodes; b. a second N-channel device having source, drain and gate electrodes; c. said drain electrode of said first N-channel device being connected to said gate electrode of said frst N-channel device and said gate electrode of said second N-channel device; d. said source electrode of said first N-channel device being connected to said source electrode of said second N-channel and to said first voltage level; e. said drain electrode of said first N-channel device being connected to said drain electrode of said first P-channel device in said input stage; and f. said drain electrode of said second N-channel device being connected to said drain electrode of said second P-channel device in said input stage for forming an output terminal.

Claim 10

A comparator as recited in claim 6, wherein said load stage furthr comprises: a. a first resistor being connected in series between said gate electrode of said first N-channel device in said load network and said drain electrode of said same device; b. a first output signal being available at the junction of said first resistor and said drain electrode of said first N-channel device; and c. a second resistor being connected in series between said gate electrode of said second N-channel device in said load network and said drain electrode of said same device.

Claim 11

A comparator as recited in claim 7, wherein said voltage shifting means comprises: a. a second N-channel device having source, drain and gate electrodes positioned intermediate said first N-channel device in said bias network and said first voltage level; b. said gate electrode of said second N-channel device forming a junction with said drain electrode of said same device and said junction being connected with said source electrode of said N-channel device in said bias networks; c. said source electrode of said second N-channel device being connected to said first voltage level. d. a third N-channel device having source, drain and gate electrodes positioned intermediate said first N-channel device in said output stage and said first voltage level; e. said gate electrode of said first N-channel device forming a junction with said drain electrode of said same device and said junction being connected with said source electrode of said first N-channel device in said input circuit; and f. said source electrode of said third N-channel device being connected to said first voltage level.

Claim 12

A comparator as recited in claim 8, wherein said voltage shifting means further comprising: a fourth N-channel device source, drain and gate electrodes positioned intermediate said load network and said first voltage level; b. said gate electrode of said third N-channel device forming a junction with said drain electrode of said same device and said junction being connected with said source electrodes of said N-channel devices in said load circuit; and c. said source electrode of said fourth N-channel device being connected to said first voltage level.

Claim 13

A comparator as recited in claim 8, wherein said voltage shifting means further comprises: a. a fourth N-channel device having source, drain and gate electrodes; b. a fifth N-channel device having source, drain and gate electrodes; c. said drain electrode of said fourth N-channel device being connected to said source electrode of said first N-channel device, and said gate electrode of said fourth N-channel device being connected to said drain electrode of said fourth N-channel device and to said gate electrode of said fifth N-channel device; and d. said drain electrode of said fifth N-channel device being connected to said source electrode of said second N-channel device and said source electrode of said fifth N-channel device being connected to said source electrode of said fourth N-channel device, and the connection of said source electrode of said fourth N-channel device and said source electrode of said fifth N-channel device being connected to said first voltage level.