← Back to Patent Explorer
US4490734A Expired / Lapsed US ⏱️ 0.0 years remaining

Variable impedance circuit employing an RIS field effect transistor

Assignee: Sony Corp
•
Filing: 1982-02-17
•
Granted: 1984-12-25
•
Expires: 2002-02-17
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A variable impedance circuit employing an RIS field effect transistor which greatly reduces distortion at low and high frequencies is obtained by providing means for applying voltages to the RIS field effect transistor at values determined by the following equations: ##EQU1## where V BG is the backgate voltage, V D is the voltage applied to the drain, V S is the voltage applied to the source, V BO is the DC component of the voltage applied to the substrate, K is a constant, α 1 is a constant, α 2 is a constant, V GS is the voltage applied to the gate at the end nearest the source, V GD is voltage applied to the gate at the end nearest the drain and V GO is a control voltage.

Inventors

  • 👤 Takaaki Yamada

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 08:31
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/189; H03F3/19; H03F3/191; H03G; H03G1/00; H03G1/0005; H03G1/0035; H03G1/007; H03H; H03H11/00; H03H11/02; H03H11/24; H03H11/245; H10; H10D; H10D64/00; H10D64/60; H10D64/605; H10D84/00; H10D84/80; H10D84/811; H10D84/817

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 222 words
A variable impedance circuit comprising a field effect transistor formed from a substrate in which a source and a drain region are formed, an insulating layer formed on said substrate between said source and drain, a resistive gate layer formed on said insulating layer between said source and drain, a first gate electrode connected to a first end of said resistive gate layer which is near said source, a second gate electrode connected to a second end of said resistive gate layer which is near said drain, a back gate electrode connected to said substrate of said field effect transistor, a voltage source connected to said back gate electrode, a first phase inverter connected to said drain, a first adder circuit including a first variable resistor connected to said first phase inverter, a control voltage source connected to said first adder and the output of said first adder connected to said second gate electrode, a second phase inverter and amplifier circuit connected to the output of said first phase inverter circuit, a second adder circuit including a second variable resistor connected to said second phase inverter circuit, the output of said second adder and said control voltage source connected to said first gate electrode, a load connected across said source and drain, and an input voltage connected across said source and drain.
Claim 2
Dependent Claim 222 words
A variable impedance circuit comprising a field effect transistor formed from a substrate in which a source and a drain region are formed, an insulating layer formed on said substrate between said source and drain, a resistive gate layer formed on said insulating layer between said source and drain, a first gate electrode connected to a first end of said resistive gate layer which is near said source, a second gate electrode connected to a second end of said resistive gate layer which is near said drain, a back gate electrode connected to said substrate of said field effect transistor, a voltage source connected to said back gate electrode, a first phase inverter connected to said drain, a first adder circuit including a first variable resistor connected to said first phase inverter, a control voltage source connected to said first adder and the output of said first adder connected to said second gate electrode, a second phase inverter and amplifier circuit connected to the output of said first phase inverter circuit, a second adder circuit including a second variable resistor connected to said second phase inverter circuit, the output of said second adder and said control voltage source connected to said first gate electrode, a load connected across said source and drain, and an input voltage connected across said source and drain.
Claim 3
Dependent Claim 21 words
A variable impedance circuit according to claim 1 including a third resistor connected between said input voltage and said drain electrode.
Claim 4
Dependent Claim 27 words
A variable impedance circuit according to claim 2 wherein a portion of the output voltage of the second phase inverter is applied to the back gate electrode.

References Cited (Backward Citations)

US3714522A Cited
US3999210A Cited
US3943286A Cited
US4157557A Cited
US3968452A Cited
US4093874A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-12-25 1988-06-25 1988-12-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-12-25 1992-06-25 1992-12-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-12-25 1996-06-25 1996-12-25 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag