US4467519A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for fabricating polycrystalline silicon film resistors
Assignee: International Business Machines Corp
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Filing: 1982-04-01
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Granted: 1984-08-28
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Expires: 2002-04-01
Abstract
Abstract A method for fabricating polycrystalline silicon resistors is described which includes deposition of a polycrystalline silicon layer of very fine grain size upon an insulator surface, followed by ion implantation of boron equal to or slightly in excess of the solubility limit of the polycrystalline silicon. This ion implantation is normally done using a screen silicon dioxide surface layer. The structure may be annealed at temperatures of between about 800 DEG C. to 1100 DEG C. for 15 to 180 minutes to control the grain size of the polycrystalline silicon layer, homogenize the distribution of the boron ions throughout the entire film thickness and to raise the concentration of the boron in the silicon grains to the solid solubility limit. The suitable electrical contacts are now made to the polycrystalline silicon layer to form the resistor.
Inventors
- 👤 Reinhard Glang
- 👤 San-Mei Ku
- 👤 Alfred Schmitt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:13
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/30; H10P32/302
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
104 words
A method for making a polycrystalline silicon resistor comprising: depositing a polycrystalline silicon layer of very fine grain size upon an insulator surface; ion implanting boron into said polycrystalline silicon layer approximately equal to or in excess of the solid solubility limit of said polycrystalline silicon at between about 3×10 19 and 3×10 20 atoms/cm 3 ; thermally annealing the said polycrystalline silicon layer at a temperature of less than about 1100° C. to control the grain size of the said polycrystalline silicon layer resistor to be between about a few nanometers and 300 nanometers; and making contacts to said layer as said resistor.
Claim 2
Independent Claim
104 words
A method for making a polycrystalline silicon resistor comprising: depositing a polycrystalline silicon layer of very fine grain size upon an insulator surface; ion implanting boron into said polycrystalline silicon layer approximately equal to or in excess of the solid solubility limit of said polycrystalline silicon at between about 3×10 19 and 3×10 20 atoms/cm 3 ; thermally annealing the said polycrystalline silicon layer at a temperature of less than about 1100° C. to control the grain size of the said polycrystalline silicon layer resistor to be between about a few nanometers and 300 nanometers; and making contacts to said layer as said resistor.
Claim 3
Dependent Claim
24 words
The method of claim 1 wherein said polycrystalline silicon is deposited by pyrolysis of silane at a temperature between about 600° to 750° C.
Claim 4
Dependent Claim
14 words
The method of claim 1 wherein said insulator surface is composed of silicon dioxide.
Claim 5
Dependent Claim
24 words
The method of claim 1 and further comprising etching the said polycrystalline silicon layer to thin said layer prior to said ion implanting boron.
Claim 6
Dependent Claim
24 words
The method of claim 1 wherein said annealing is done at a temperature between about 800° to 1100° C. for 15 to 180 minutes.
Claim 7
Dependent Claim
21 words
The method of claim 3 wherein said silicon dioxide forms a part of the dielectric isolation of an integrated circuit structure.
Claim 8
Dependent Claim
30 words
The method of claim 6 wherein said polycrystalline silicon layer is formed simultaneously with an extrinsic polycrystalline silicon contact layer base on the extrinsic base region of a bipolar transistor.
Claim 9
Dependent Claim
22 words
The method of claim 7 wherein said ion implantation is simultaneously done into said extrinsic base and said polycrystalline silicon resistor layer.
Claim 10
Dependent Claim
20 words
The method of claim 8 wherein the average said grain size after said annealing is less than about 150 nanometers.
Claim 11
Dependent Claim
69 words
The method of claim 7 wherein said annealing is done at a temperature between about 800° to 1100° C. for 15 to 180 minutes to simultaneously drive in the said boron from the external base contact into the monocrystalline silicon extrinsic base and to homogenize the distribution of said boron atoms and raise the concentration of said boron in the silicon grains to the solubility limit of said resistor.
Claim 12
Dependent Claim
27 words
The method of claim 4 wherein said etching is by reactive ion etching and said layer is thinned to a layer of less than about 50 nanometers.
Claim 13
Independent Claim
166 words
The method of forming an integrated circuit which includes an NPN transistor and a resistor comprising: providing a silicon semiconductor body having regions of monocrystalline silicon dielectrically isolated from one another by dielectric isolating regions; providing a mask over the surface of said body having said isolating regions therein covering all regions except those regions designated to be the extrinsic base regions; depositing a polycrystalline silicon layer of very fine grain size over the said mask and said designated extrinsic base regions; ion implanting boron equal to or in excess of the solid solubility limit of said polycrystalline silicon; thermally annealing the said polycrystalline silicon layer to simultaneously control the grain size in said layer and drive in the said boron from the said layer into said designated external base region; removing portions of said polycrystalline silicon layer by lithography and etching to delineate external base contact and resistors in said polycrystalline silicon layer; and making contacts to said external base contacts and to said resistors.
Claim 14
Independent Claim
166 words
The method of forming an integrated circuit which includes an NPN transistor and a resistor comprising: providing a silicon semiconductor body having regions of monocrystalline silicon dielectrically isolated from one another by dielectric isolating regions; providing a mask over the surface of said body having said isolating regions therein covering all regions except those regions designated to be the extrinsic base regions; depositing a polycrystalline silicon layer of very fine grain size over the said mask and said designated extrinsic base regions; ion implanting boron equal to or in excess of the solid solubility limit of said polycrystalline silicon; thermally annealing the said polycrystalline silicon layer to simultaneously control the grain size in said layer and drive in the said boron from the said layer into said designated external base region; removing portions of said polycrystalline silicon layer by lithography and etching to delineate external base contact and resistors in said polycrystalline silicon layer; and making contacts to said external base contacts and to said resistors.
Claim 15
Dependent Claim
15 words
The method of claim 12 wherein said resistors are located over said dielectric isolating regions.
Claim 16
Dependent Claim
27 words
The method of claim 12 wherein said polycrystalline silicon layer is partially thermally oxidized before said ion implanting boron to act as a screen silicon dioxide layer.
Claim 17
Dependent Claim
28 words
The method of claim 12 wherein the boron concentration in resulting said polycrystalline silicon layer is between about 3×10 19 atoms/cm 3 to 3×10 20 atoms/cm 3 .
Claim 18
Dependent Claim
19 words
The method of claim 12 wherein the said grain size after said annealing is less than about 150 nanometers.
Claim 19
Dependent Claim
34 words
The method of claim 14 wherein the said thickness polycrystalline silicon layer is between about 30 to 500 nanometers and the thickness of said silicon dioxide layer is between about 20 to 100 nanometers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-28 | 1988-02-27 | 1988-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-28 | 1992-02-27 | 1992-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-28 | 1996-02-27 | 1996-08-28 | $7700.00 | Window Closed / Lapsed |