US4411708A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making precision doped polysilicon vertical ballast resistors by multiple implantations
Assignee: Motorola Solutions Inc
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Filing: 1980-08-25
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Granted: 1983-10-25
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Expires: 2000-08-25
Abstract
Abstract The structure and associated fabrication processes disclosed provide a resistive element directly over a specific semiconductor region. Use of such a structure in a high current device ballasts emitter fingers to improve the maximum current flow of the device. The resistor element includes polysilicon which has conductivity affecting impurities in it with concentration less than 10 20 atom/cm 3 , and typically 10 17 to 10 19 atom/cm 3 , to create a resistivity of generally 0.05 to 5 ohm-cm. Such a resistive element may be formed by plural implants into the polysilicon, with subsequent annealing; by smoothly varying, typically between 10 keV and 300 keV, the implant energy during implanting; by implanting an appropriate impurity into doped polysilicon to adjust the effective impurity concentration; or by backdiffusing an impurity from a heavily doped region into the overlaying polysilicon.
Inventors
- 👤 Lucien C. Winhan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:37
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D84/00; H10D84/101; H10D84/121; H10D84/125; H10P; H10P32/00; H10P32/30; H10P32/302; Y; Y10; Y10S; Y10S148/00; Y10S148/092
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
114 words
A process for forming a vertical polysilicon resistor directly over and in electrical contact with a portion of the surface of a semiconductor device, comprising the steps of: providing an electrically nonconductive mask to define the surface portion; depositing a layer of polysilicon over the surface portion; ion implanting into the polysilicon at plural discrete energy levels at least one conductivity affecting impurity; annealing the semiconductor device to form a more uniform effective dopant concentration in the polysilicon in the range 10 17 to 10 19 atoms/cm 3 ; and forming an electrical connection to the top of the polysilicon, thereby forming a resistor directly over and in electrical contact with the surface portion.
Claim 2
Dependent Claim
114 words
A process for forming a vertical polysilicon resistor directly over and in electrical contact with a portion of the surface of a semiconductor device, comprising the steps of: providing an electrically nonconductive mask to define the surface portion; depositing a layer of polysilicon over the surface portion; ion implanting into the polysilicon at plural discrete energy levels at least one conductivity affecting impurity; annealing the semiconductor device to form a more uniform effective dopant concentration in the polysilicon in the range 10 17 to 10 19 atoms/cm 3 ; and forming an electrical connection to the top of the polysilicon, thereby forming a resistor directly over and in electrical contact with the surface portion.
Claim 3
Dependent Claim
21 words
A process according to claim 1 wherein the step of depositing forms a polysilicon layer generally 100 to 10,000 Angstroms thick.
Claim 4
Dependent Claim
16 words
A process according to claim 1 wherein the step of implanting uses plural conductivity affecting impurities.
Claim 5
Dependent Claim
15 words
A process according to claim 1 wherein the polysilicon being deposited includes conductivity affecting impurities.
Claim 6
Dependent Claim
35 words
A process according to claim 4 wherein the step of implanting impurities into the deposited polysilicon uses an impurity of opposite conductivity type than that in the deposited polysilicon, thereby lowering the effective carrier concentration.
Claim 7
Dependent Claim
112 words
A process for forming a vertical polysilicon resistor directly over and in electrical contact with a portion of the surface of a semiconductor device, comprising the steps of: providing an electrically nonconductive mask to define the surface portion; depositing a layer of polysilicon over the surface portion; ion implanting in the polysilicon a conductivity affecting impurity, the implant energy smoothly varying during the implanting to obtain a nongaussian dopant distribution in the polysilicon, with an average impurity concentration between 10 17 and 10 19 atoms/cm 3 ; and forming an electrical connection to the top of the polysilicon, thereby forming a resistor directly over and in electrical contact with the surface portion.
Claim 8
Dependent Claim
112 words
A process for forming a vertical polysilicon resistor directly over and in electrical contact with a portion of the surface of a semiconductor device, comprising the steps of: providing an electrically nonconductive mask to define the surface portion; depositing a layer of polysilicon over the surface portion; ion implanting in the polysilicon a conductivity affecting impurity, the implant energy smoothly varying during the implanting to obtain a nongaussian dopant distribution in the polysilicon, with an average impurity concentration between 10 17 and 10 19 atoms/cm 3 ; and forming an electrical connection to the top of the polysilicon, thereby forming a resistor directly over and in electrical contact with the surface portion.
Claim 9
Dependent Claim
19 words
A process according to claim 6 wherein the implant energy varies in the range 10 keV to 300 keV.
Claim 10
Dependent Claim
21 words
A process according to claim 7 wherein the implant energy is varied to implant the impurity generally uniformly throughout the polysilicon.
Claim 11
Dependent Claim
100 words
A process for forming a vertical polysilicon resistor over and in electrical contact with a portion of the surface of a semiconductor device having a high concentration of conductivity affecting impurity comprising: providing an electrically nonconductive mask to define the surface portion; depositing a layer of polysilicon over the surface portion; heating the semiconductor device to diffuse the impurities from the surface portion back into the overlying polysilicon to form an effective dopant concentration in the polysilicon in the range 10 17 to 10 19 atoms/cm 3 ; and forming an electrical connection to the top of the polysilicon layer.
Claim 12
Dependent Claim
100 words
A process for forming a vertical polysilicon resistor over and in electrical contact with a portion of the surface of a semiconductor device having a high concentration of conductivity affecting impurity comprising: providing an electrically nonconductive mask to define the surface portion; depositing a layer of polysilicon over the surface portion; heating the semiconductor device to diffuse the impurities from the surface portion back into the overlying polysilicon to form an effective dopant concentration in the polysilicon in the range 10 17 to 10 19 atoms/cm 3 ; and forming an electrical connection to the top of the polysilicon layer.
Claim 13
Dependent Claim
31 words
A process according to claim 9 wherein after the heating step is performed the step of ion implanting into the polysilicon conductivity affecting impurities to adjust the resistivity of the polysilicon.
Claim 14
Dependent Claim
105 words
A process for forming a vertical polysilicon resistor directly over and in electrical contact with a portion of the surface of a semiconductor device and having a high precision resistivity between 0.05 ohm-cm and 5 ohm-cm, comprising the steps of: providing an electrically non-conductive mask to define the surface portion; depositing a layer of polysilicon over the surface portion; disposing in the polysilicon a conductivity affecting impurity to achieve a first level resistivity; ion implanting in the polysilicon a conductivity affecting material to adjust the first resistivity level as necessary to achieve the particular desired resistivity in the range of 0.05 ohm-cm to 5 ohm-cm.
Claim 15
Dependent Claim
105 words
A process for forming a vertical polysilicon resistor directly over and in electrical contact with a portion of the surface of a semiconductor device and having a high precision resistivity between 0.05 ohm-cm and 5 ohm-cm, comprising the steps of: providing an electrically non-conductive mask to define the surface portion; depositing a layer of polysilicon over the surface portion; disposing in the polysilicon a conductivity affecting impurity to achieve a first level resistivity; ion implanting in the polysilicon a conductivity affecting material to adjust the first resistivity level as necessary to achieve the particular desired resistivity in the range of 0.05 ohm-cm to 5 ohm-cm.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-24 | 1987-04-25 | 1987-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-24 | 1991-04-25 | 1991-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-24 | 1995-04-25 | 1995-10-25 | $7700.00 | Window Closed / Lapsed |