US4266236A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor having emitter resistors for stabilization at high power operation
Assignee: NEC Corp
•
Filing: 1979-04-24
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Granted: 1981-05-05
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Expires: 1999-04-24
Abstract
Abstract A technique of increasing the safe operating area of a power transistor is disclosed which comprises the addition of a resistive region of a conductivity (P or N) opposite that of the emitter conductivity, the resistive region located between the emitter region and the emitter electrode so as to prevent local thermal runaway of the emitter current and the concomitant secondary breakdown of the transistor. A conducting electrode connects the emitter region to the resistive region to thereby short-circuit the resistive-emitter region junction.
Inventors
- 👤 Kazuyoshi Ueda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 01:51
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D10/056; H10D10/058; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10D84/00; H10D84/101; H10D84/121; H10D84/125; Y; Y10; Y10S; Y10S257/00; Y10S257/914
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
91 words
A semiconductor device comprising a collector region of one conductivity type, a base region of the other conductivity type making contact with said collector region, an emitter region of said one conductivity type making contact with said base region and separated from said collector region, an additional region of said other conductivity type having its pheriphery surrounded by said emitter region, an emitter electrode electrically connected to said additional region, and at least one additional electrode separated from said emitter electrode and electrically short-circuiting said emitter region and said additional region.
Claim 2
Dependent Claim
91 words
A semiconductor device comprising a collector region of one conductivity type, a base region of the other conductivity type making contact with said collector region, an emitter region of said one conductivity type making contact with said base region and separated from said collector region, an additional region of said other conductivity type having its pheriphery surrounded by said emitter region, an emitter electrode electrically connected to said additional region, and at least one additional electrode separated from said emitter electrode and electrically short-circuiting said emitter region and said additional region.
Claim 3
Dependent Claim
60 words
A semiconductor device as claimed in claim 1, wherein said collector region, said base region, said emitter region and said additional region are formed in a semiconductor substrate having a major surface, said base region, said emitter region and said additional region reaching said major surface, and said emitter electrode and said additional electrode being formed on said major surface.
Claim 4
Dependent Claim
43 words
A semiconductor device claimed in claim 2, further comprising a base electrode connected to said base region at said major surface and a collector electrode attached to said collector region at a surface of said substrate which is opposite to said major surface.
Claim 5
Dependent Claim
31 words
A semiconductor device in claims 1 or 2, wherein a portion of said additional region between said emitter electrodes and said additional electrode has a resistance of 0.03 to 0.2 ohms.
Claim 6
Dependent Claim
106 words
A semiconductor device comprising a first region of one conductivity type, a second region of the other conductivity type formed in said first region, a third region of said one conductivity type formed in said second region, a fourth region of said other conductivity type formed in said third region, a first means coupled to said fourth region for leading out a common terminal, a second means coupled to said third and fourth regions for shortcircuitting therebetween, a third means coupled to said second region for leading out a control terminal, and a fourth means coupled to said first region for leading out an output terminal.
Claim 7
Dependent Claim
106 words
A semiconductor device comprising a first region of one conductivity type, a second region of the other conductivity type formed in said first region, a third region of said one conductivity type formed in said second region, a fourth region of said other conductivity type formed in said third region, a first means coupled to said fourth region for leading out a common terminal, a second means coupled to said third and fourth regions for shortcircuitting therebetween, a third means coupled to said second region for leading out a control terminal, and a fourth means coupled to said first region for leading out an output terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-05-04 | 1984-11-03 | 1985-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-05-04 | 1988-11-03 | 1989-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-05-04 | 1992-11-03 | 1993-05-05 | $7700.00 | Window Closed / Lapsed |