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US3893154A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor arrangement with current stabilizing resistance

Assignee: Telefunken Electronic GmbH
•
Filing: 1973-10-19
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Granted: 1975-07-01
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Expires: 1993-10-19
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Abstract

Abstract A semiconductor arrangement comprises two regions of different types of conductivity in a semiconductor body, one of the regions forming a pn junction which extends to a surface of the semiconductor body on which an insulating layer is provided, a ohmic contact on this said latter region only along its entire edge and a resistance between the ohmic contact and a current feed contact for said latter region.

Inventors

  • 👤 Werner Mroczek
  • 👤 Josef Wolf

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 01:32
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/101; H10D84/121; H10D64/00; H10D64/20; H10P; H10P95/00; H10W; H10W20/00; H10W20/40; H10W20/482; H10W20/484

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 166 words
In a semiconductor device including a semiconductor body having at least two regions of alternatingly opposite conductivity type with at least one of said regions forming a pn junction which extends to a major surface of said semiconductor body, an insulating layer on said major surface, and a contact ohmically connected to said one region via an aperture in said insulating layer, the improvement wherein said contact is formed of resistance material, is connected to said one region only at its outer edge and extends along the entire length of said edge of said one region; and further comprising a current feed terminal for said one region connected to said contact by a resistance formed of a coherent layer of resistance material on said insulating layer, said current feed terminal being connected to said layer of resistance material at a position such that the shortest spacing between said current feed terminal and said contact via said layer of resistance material is the same at all points.
Claim 2
Dependent Claim 166 words
In a semiconductor device including a semiconductor body having at least two regions of alternatingly opposite conductivity type with at least one of said regions forming a pn junction which extends to a major surface of said semiconductor body, an insulating layer on said major surface, and a contact ohmically connected to said one region via an aperture in said insulating layer, the improvement wherein said contact is formed of resistance material, is connected to said one region only at its outer edge and extends along the entire length of said edge of said one region; and further comprising a current feed terminal for said one region connected to said contact by a resistance formed of a coherent layer of resistance material on said insulating layer, said current feed terminal being connected to said layer of resistance material at a position such that the shortest spacing between said current feed terminal and said contact via said layer of resistance material is the same at all points.
Claim 3
Dependent Claim 23 words
A semiconductor arrangement as defined in claim 1, wherein said at least one region comprises a planar type emitter region of a transistor.
Claim 4
Dependent Claim 46 words
A semiconductor arrangement as defined in claim 2, wherein the part of said insulating layer covering said emitter region surrounded by said contact is covered with said layer of resistance material and said current feed terminal is arranged in a centre position on this resistance layer.
Claim 5
Dependent Claim 26 words
A semiconductor arrangement as defined in claim 3, wherein the resistance material of said ohmic contact and said resistance layer covering said insulating layer comprises nickel-chromium.
Claim 6
Dependent Claim 29 words
A semiconductor arrangement as defined in claim 2, wherein the resistance between said emitter contact and said emitter current feed terminal has a value of between approximately 10-100 mOhm.
Claim 7
Dependent Claim 28 words
A semiconductor arrangement as defined in claim 2, wherein said at least one region which is on the outer edge is the emitter region of a power transistor.
Claim 8
Dependent Claim 19 words
A semiconductor arrangement as defined in claim 3 wherein said emitter region is circular and said contact is annular.

References Cited (Backward Citations)

US3256587A Cited
US3358197A Cited
US3504239A Cited
US3462658A Cited
US3562607A Cited
US3585414A Cited
US3614480A Cited
US3600646A Cited
US3667008A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-06-30 1978-12-30 1979-07-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-06-30 1982-12-30 1983-07-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-06-30 1986-12-30 1987-07-01 $7700.00 Window Closed / Lapsed

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