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US3936863A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated power transistor with ballasting resistance and breakdown protection

Assignee: RCA Corp
•
Filing: 1974-09-09
•
Granted: 1976-02-03
•
Expires: 1994-09-09
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Abstract

Abstract An integrated power transistor has at least one emitter region, having a ballasting resistance to reduce the possibility of second breakdown. Also integrated within the device is a voltage control diode, located between the collector terminal and the emitter terminal, to protect against high voltages caused by transient surges, particularly during switching times.

Inventors

  • 👤 John Aaron Olmstead

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 09:58
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/101; H10D84/121; H10D84/125; H10D84/60; H10D84/611; H10D84/613

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 208 words
An integrated semiconductor device having resistor ballasting and having reverse bias breakdown protection comprising; a body of semiconductor material having one type conductivity and having at least a first and a second surface, at least one first region, having a second type conductivity, adjacent said first surface and forming an equal number of first PN junctions at the interface therebetween, at least one second region, having said second type conductivity, adjacent said first surface, and forming at least one second PN junction at the interface with said body of semiconductor material and being spaced apart from said first region thereby, at least one third region, having said one type conductivity, within said first region and separated from said body of semiconductor material thereby, said third region and said first region have a third PN junction at their interface, a plurality of jumper means, insulatingly disposed over said body of semiconductor material, providing electrical paths from said second region to said third region, first terminal means providing electrical contact to said body of semiconductor material, second terminal means providing electrical contact to said first region, and third terminal means providing electrical contact to said second region, said third terminal means being spaced apart from said plurality of jumper means.
Claim 2
Dependent Claim 208 words
An integrated semiconductor device having resistor ballasting and having reverse bias breakdown protection comprising; a body of semiconductor material having one type conductivity and having at least a first and a second surface, at least one first region, having a second type conductivity, adjacent said first surface and forming an equal number of first PN junctions at the interface therebetween, at least one second region, having said second type conductivity, adjacent said first surface, and forming at least one second PN junction at the interface with said body of semiconductor material and being spaced apart from said first region thereby, at least one third region, having said one type conductivity, within said first region and separated from said body of semiconductor material thereby, said third region and said first region have a third PN junction at their interface, a plurality of jumper means, insulatingly disposed over said body of semiconductor material, providing electrical paths from said second region to said third region, first terminal means providing electrical contact to said body of semiconductor material, second terminal means providing electrical contact to said first region, and third terminal means providing electrical contact to said second region, said third terminal means being spaced apart from said plurality of jumper means.
Claim 3
Dependent Claim 61 words
An integrated semiconductor device having resistor ballasting and having reverse bias breakdown protection as claimed in claim 1 wherein; said body of semiconductor material contains a lower portion and an upper portion, said lower portion having a higher carrier concentration than said upper portion, said lower portion being adjacent said second surface and said upper portion being adjacent said first surface.
Claim 4
Dependent Claim 39 words
An integrated semiconductor device having resistor ballasting and having reverse bias breakdown protection as claimed in claim 1 wherein; each one of said jumper means is connected from a single said second region to a single said third region.
Claim 5
Dependent Claim 27 words
An integrated semiconductor device having resistor ballasting and having reverse bias breakdown protection as claimed in claim 1 wherein; said second region has a non-negative thermal coefficient.
Claim 6
Dependent Claim 51 words
An integrated semiconductor device having resistor ballasting and having reverse bias breakdown protection as claimed in claim 1 wherein; said resistor ballasting is located between said third region and said third terminal means whereby the ohmic value of said resistor ballasting is dependent on the sheet resistivity of said second region.
Claim 7
Dependent Claim 36 words
An integrated semiconductor device having resistor ballasting and having reverse bias breakdown protection as claimed in claim 1 wherein; said second PN junction constitutes a voltage control diode, said diode providing said reverse bias breakdown protection.
Claim 8
Dependent Claim 37 words
An integrated semiconductor device having resistor ballasting and having reverse bias breakdown protection as claimed in claim 6 wherein; said voltage control diode has a breakdown voltage less then the breakdown voltage of said first PN junction.
Claim 9
Dependent Claim 48 words
An integrated semiconductor device having resistor ballasting and having reverse bias breakdown protection as claimed in claim 1 wherein; said body of semiconductor material contains at least one mesa with sidewalls and each second PN junction terminates at said first surface and at said sidewalls of said mesa.

References Cited (Backward Citations)

US3435295A Cited
US3510771A Cited
US3609460A Cited
US3577062A Cited
US3619741A Cited
US3740621A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-02-02 1979-08-04 1980-02-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-02-02 1983-08-04 1984-02-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-02-02 1987-08-04 1988-02-03 $7700.00 Window Closed / Lapsed

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