Patent US5605515A successfully refreshed from Google Patents.
US4352997A
Expired / Lapsed
US
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Static MOS memory cell using inverted N-channel field-effect transistor
Assignee: Texas Instruments Inc
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Filing: 1979-02-12
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Granted: 1982-10-05
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Expires: 1999-02-12
Abstract
Abstract A storage cell employs two conventional N-channel MOS transistors and an inverted N-channel field-effect transistor along with an implanted polysilicon resistor and a resistor implanted under field oxide which functions as a junction field effect transistor. All of the transistors and a storage node as well as a voltage supply line are in one continuous moat region for a dense layout with a minimum of contacts. One MOS transistor is the access device connected between a bit line and the storage node with its gate connected to an address line. The other MOS transistor connects the storage node to the supply line and has its gate controlled by a second node which is connected to the supply line by a polycrystalline silicon strip which is the source-to-drain path of the inverted field-effect transistor; the gate of this device is a part of the moat which forms the storage node.
Inventors
- 👤 Joseph H. Raymond, Jr.
- 👤 Keith H. Gudger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:11
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/402; G11C11/41; G11C11/412; H; H10; H10B; H10B10/00; H10B10/15
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
197 words
A semiconductor integrated circuit formed at a face of a semiconductor body comprising first and second insulated-gate field-effect transistors each having a source-drain path and a gate, the source-drain path of the first transistor being connected between a first node and a source of logic levels, the gate of the first transistor being connected to a different source of logic levels the source-drain path of the second transistor being connected between the first node and voltage supply means, the gate of the second transistor being connected to a second node, first conductive means exhibiting at least some impedance connecting the first node to the second node, second conductive means exhibiting at least some impedance connecting the first node to reference potential, third conductive means connecting the second node to voltage supply means, the third conductive means exhibiting a low impedance state when the voltage on the first node is near that of the voltage supply means and exhibiting a high impedance state when the voltage on the first node is near that of the reference potential, at least one of the first, second and third conductive means being formed wholly in a deposited layer on said face.
Claim 2
Dependent Claim
197 words
A semiconductor integrated circuit formed at a face of a semiconductor body comprising first and second insulated-gate field-effect transistors each having a source-drain path and a gate, the source-drain path of the first transistor being connected between a first node and a source of logic levels, the gate of the first transistor being connected to a different source of logic levels the source-drain path of the second transistor being connected between the first node and voltage supply means, the gate of the second transistor being connected to a second node, first conductive means exhibiting at least some impedance connecting the first node to the second node, second conductive means exhibiting at least some impedance connecting the first node to reference potential, third conductive means connecting the second node to voltage supply means, the third conductive means exhibiting a low impedance state when the voltage on the first node is near that of the voltage supply means and exhibiting a high impedance state when the voltage on the first node is near that of the reference potential, at least one of the first, second and third conductive means being formed wholly in a deposited layer on said face.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-10-04 | 1986-04-05 | 1986-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-10-04 | 1990-04-05 | 1990-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-10-04 | 1994-04-05 | 1994-10-05 | $7700.00 | Window Closed / Lapsed |