US4139786A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Static MOS memory cell using inverted N-channel field-effect transistor
Assignee: Texas Instruments Inc
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Filing: 1977-05-31
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Granted: 1979-02-13
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Expires: 1997-05-31
Abstract
Abstract A storage cell employs two conventional N-channel MOS transistors and an inverted N-channel field-effect transistor along with an implanted polysilicon resistor and a resistor implanted under field oxide which functions as a junction field effect transistor. All of the transistors and a storage node as well as a voltage supply line are in one continuous moat region for a dense layout with a minimum of contacts. One MOS transistor is the access device connected between a bit line and the storage node with its gate connected to an address line. The other MOS transistor connects the storage node to the supply line and has its gate controlled by a second node which is connected to the supply line by a polycrystalline silicon strip which is the source-to-drain path of the inverted field-effect transistor; the gate of this device is a part of the moat which forms the storage node.
Inventors
- 👤 Joseph H. Raymond, Jr.
- 👤 Keith H. Gudger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:30
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/402; G11C11/41; G11C11/412; H; H10; H10B; H10B10/00; H10B10/15
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
164 words
A semiconductor integrated circuit comprising first and second MOS transistors each having a source-drain path and a gate, the source-drain path of the first transistor being connected between a first node and a source of logic levels, the gate of the first transistor being connected to a different source of logic levels, the source-drain path of the second transistor being connected between the first node and a voltage supply, the gate of the second transistor being connected to a second node, means exhibiting substantial impedance connecting the first node to the second node, an impedance element connecting the second node to the voltage supply, the impedance element exhibiting a low impedance state when the voltage on the first node is of a first level and exhibiting a high impedance state when the voltage on the first node is of a second level, the first level being substantially different in voltage from the second level, and impedance means connecting the first node to reference potential.
Claim 2
Dependent Claim
164 words
A semiconductor integrated circuit comprising first and second MOS transistors each having a source-drain path and a gate, the source-drain path of the first transistor being connected between a first node and a source of logic levels, the gate of the first transistor being connected to a different source of logic levels, the source-drain path of the second transistor being connected between the first node and a voltage supply, the gate of the second transistor being connected to a second node, means exhibiting substantial impedance connecting the first node to the second node, an impedance element connecting the second node to the voltage supply, the impedance element exhibiting a low impedance state when the voltage on the first node is of a first level and exhibiting a high impedance state when the voltage on the first node is of a second level, the first level being substantially different in voltage from the second level, and impedance means connecting the first node to reference potential.
Claim 3
Dependent Claim
29 words
A circuit according to claim 1 wherein the impedance element is a polycrystalline silicon layer overlying a face of a body of material and has a low impurity concentration.
Claim 4
Dependent Claim
23 words
A circuit according to claim 2 wherein the layer overlies a moat region providing the first node separated therefrom by thin silicon oxide.
Claim 5
Dependent Claim
51 words
A circuit according to claim 2 wherein the source of logic levels is a bit line in a memory array, the different source of logic levels in an address line in the memory array, and the first node is a storage node capable of sustaining a logic "1" or logic "0".
Claim 6
Dependent Claim
119 words
A storage cell comprising an address line, a data line, a storage node, a first controlled switching device having a current path connecting the data line to the storage node and being controlled by the address line, a voltage supply, a second controlled switching device having a control element and having a current path connecting the storage node to the voltage supply, means exhibiting significant impedance connecting the storage node to a second node, the second node being connected to the control element of the second switching device, voltage-controlled impedance means connecting the voltage supply to the second node and controlled by the voltage on the storage node, and second impedance means connecting the storage node to reference potential.
Claim 7
Dependent Claim
119 words
A storage cell comprising an address line, a data line, a storage node, a first controlled switching device having a current path connecting the data line to the storage node and being controlled by the address line, a voltage supply, a second controlled switching device having a control element and having a current path connecting the storage node to the voltage supply, means exhibiting significant impedance connecting the storage node to a second node, the second node being connected to the control element of the second switching device, voltage-controlled impedance means connecting the voltage supply to the second node and controlled by the voltage on the storage node, and second impedance means connecting the storage node to reference potential.
Claim 8
Dependent Claim
33 words
A storage cell according to claim 5 wherein the controlled switching devices are MOS transistors and the voltage-controlled impedance means is an inverted field effect transistor having its source-to-drain path overlying its gate.
Claim 9
Dependent Claim
18 words
A storage cell according to claim 6 wherein the inverted field effect transistor is of the N-channel type.
Claim 10
Dependent Claim
21 words
A storage cell according to claim 6 wherein the gate is a moat region in a face of a semiconductor body.
Claim 11
Dependent Claim
33 words
A storage cell according to claim 8 wherein one continuous moat region provides the voltage supply line, the storage node, the source-to-drain paths of the first and second switching devices, and said gate.
Claim 12
Dependent Claim
44 words
A storage cell according to claim 5 wherein the cell is within a semiconductor integrated circuit and the voltage-controlled impedance means is formed by an elongated polycrystalline silicon region overlying the face of a body of semiconductor material but has low net impurity concentration.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-12 | 1982-08-14 | 1983-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-12 | 1986-08-14 | 1987-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-12 | 1990-08-14 | 1991-02-13 | $7700.00 | Window Closed / Lapsed |