Switched capacitor non-volatile mnos random access memory cell

Claim 2

An MOS random-access integrated circuit memory cell which utilizes at least separate read-refresh, input-output, write, and addressing lines comprising: a two terminal switched capacitor adapted for storing an electrical charge, having one of its terminals coupled to the read-refresh line; a first alterable threshold MOS device having a gate coupled to the write line and at least two other electrodes, one of the other electrodes coupled to the other terminal of the switched capacitor, the other electrode coupled to a common junction; a first storage capacitor coupled between a first source of reference potential and the common junction; a second MOS device having a gate coupled to the other terminal of the switched capacitor and at least two other electrodes, one of the other electrodes coupled to the common junction, the other electrode coupled to a source of operating potential; a third MOS device having a gate coupled to the addressing line and at least two other electrodes, one of the other electrodes coupled to the common junction, the other electrode coupled to the input-output line; and a second storage capacitor coupled between a second source of reference potential and the other terminal of the switched capacitor to allow the switched capacitor to couple the readrefresh line to the first MOS device during intervals the second capacitor is charged above a given value and to allow the switched capacitor to disconnect the read-refresh line from the first MOS device during intervals the second capacitor is chargEd below the given value.

Claim 3

The cell of claim 1 wherein the first MOS device stores information therein when operating potential is removed.

Claim 4

The cell of claim 2 wherein the first MOS device is a metal-nitride-oxide-semiconductor.

Claim 5

The cell of claim 2 wherein the first and second storage capacitors are the parasitic capacitances between the cell and a substrate supporting the cell.

Claim 6

An MOS random-access integrated circuit memory cell which utilizes at least separate read-refresh, input-output, write, and addressing lines comprising: a body of semiconductor material supported on a substrate; a gate and a drain region in the semiconductor material defining a two terminal switched capacitor adapted for storing an electrical charge, having the drain region coupled to the read-refresh line; a first alterable threshold MOS device having a gate, a source region and a drain region, wherein the gate is coupled to the write line, the source region is coupled to the gate of the switched capacitor and the drain region is coupled to a common junction; a first storage capacitor coupled between a first source of reference potential and the common junction; a second MOS device having a gate, a source region and a drain region wherein the gate is coupled to the gate of the switched capacitor, the source region is coupled to the common junction and the drain region is coupled to a source of operating potential; a third MOS device having a gate, a source region and a drain region, wherein the gate is coupled to the addressing line, the drain region is coupled to the common junction and the source region is coupled to the input-output line; and a second storage capacitor coupled between a second source of reference potential and the gate of the switched capacitor to allow the switched capacitor to couple the read-refresh line to the first MOS device during intervals the second capacitor is charged above a given value and to allow the switched capacitor to disconnect the read-refresh line from the first MOS device during intervals the second capacitor is charged below the given value.

Claim 7

An MOS random-access integrated circuit memory cell which utilizes at least separate read-refresh, input-output, write, and addressing lines comprising: a body of semiconductor material supported on a substrate; a gate and a drain region in the semiconductor material defining a two terminal switched capacitor adapted for storing an electrical charge, having the drain region coupled to the read-refresh line; a first alterable threshold MOS device having a gate, a source region and a drain region, wherein the gate is coupled to the write line, the source region is coupled to the gate of the switched capacitor and the drain region is coupled to a common junction; a first storage capacitor coupled between a first source of reference potential and the common junction; a second MOS device having a gate, a source region and a drain region wherein the gate is coupled to the gate of the switched capacitor, the source region is coupled to the common junction and the drain region is coupled to a source of operating potential; a third MOS device having a gate, a source region and a drain region, wherein the gate is coupled to the addressing line, the drain region is coupled to the common junction and the source region is coupled to the input-output line; and a second storage capacitor coupled between a second source of reference potential and the gate of the switched capacitor to allow the switched capacitor to couple the read-refresh line to the first MOS device during intervals the second capacitor is charged above a given value and to allow the switched capacitor to disconnect the read-refresh line from the first MOS device during intervals the second capacitor is charged below the given value.

Claim 8

An array of MOS random-access integrated circuit memory cells arranged in columns and rows, the array utilizing at least separate read-refresh, input-output, write, and addressing lines comprising: a two terminal switched capacitor associated with each cell capacitor adapted for storing an electrical charge and having one of its terminals coupled to the read-refresh line; a first alterable threshold MOS device associated with each cell, each such device having a gate coupled to the write line and at least two other electrodes, one of the other electrodes coupled to the other terminal of the switched capacitor of the cell, the other electrode coupled to a common junction of the cell; a first storage capacitor coupled between a first source of reference potential and the common junction; a second MOS device associated with each cell, such device having a gate coupled to the other terminal of the switched capacitor and at least two other electrodes, one of the other electrodes coupled to the common junction, the other electrode coupled to a source of operating potential; a third MOS device associated with each cell, each such device having a gate and at least two other electrodes, the gate of each such third MOS device in a cell in a given row coupled to respective ones of a plurality of addressing lines, one of the other electrodes coupled to the common junction, the other electrode of each such third MOS device in a cell in a given column coupled to respective ones of a plurality of input-output lines; and a second storage capacitor associated with each cell and coupled between a second source of reference potential and the other terminal of the switched capacitor to allow the switched capacitor to couple the read-refresh line to each of the first MOS devices of each cell during intervals the seconD capacitor is charged above a given value and to allow the switched capacitor to disconnect the read-refresh line from the first MOS device during intervals the second capacitor is charged below the given value.

Claim 9

An array of MOS random-access integrated circuit memory cells arranged in columns and rows, the array utilizing at least separate read-refresh, input-output, write, and addressing lines comprising: a two terminal switched capacitor associated with each cell capacitor adapted for storing an electrical charge and having one of its terminals coupled to the read-refresh line; a first alterable threshold MOS device associated with each cell, each such device having a gate coupled to the write line and at least two other electrodes, one of the other electrodes coupled to the other terminal of the switched capacitor of the cell, the other electrode coupled to a common junction of the cell; a first storage capacitor coupled between a first source of reference potential and the common junction; a second MOS device associated with each cell, such device having a gate coupled to the other terminal of the switched capacitor and at least two other electrodes, one of the other electrodes coupled to the common junction, the other electrode coupled to a source of operating potential; a third MOS device associated with each cell, each such device having a gate and at least two other electrodes, the gate of each such third MOS device in a cell in a given row coupled to respective ones of a plurality of addressing lines, one of the other electrodes coupled to the common junction, the other electrode of each such third MOS device in a cell in a given column coupled to respective ones of a plurality of input-output lines; and a second storage capacitor associated with each cell and coupled between a second source of reference potential and the other terminal of the switched capacitor to allow the switched capacitor to couple the read-refresh line to each of the first MOS devices of each cell during intervals the seconD capacitor is charged above a given value and to allow the switched capacitor to disconnect the read-refresh line from the first MOS device during intervals the second capacitor is charged below the given value.

Claim 10

The cell of claim 6 wherein the first MOS device of each cell of the array stores information therein when operating potential is removed.

Claim 11

The cell of claim 7 wherein the first MOS device of each cell of the array is a metal-nitride-oxide-semi-conductor.

Claim 12

The cell of claim 7 wherein the first and second storage capacitors of each cell of the array are the parasitic capacitances between the cell and a substrate supporting the cell.