Solid state memory array

Claim 2

A digital memory circuit comprising an array of rows and columns of memory elements formed on a common substrate, each of said memory elements including a variable threshold insulated gate field effect transistor having drain and source electrodes and a gate electrode separated from said substrate by a gate insulator, means to drive all of said transistors to a first threshold, means to drive selected transistors to a second oppositely-polarized threshold in accordance with information to be stored, means to apply a sampling potential across the gate insulator of all of the transistors in a selected row, said sampling potential having a polarity such as to form a conducting channel in the transistors that remain at their first threshold, means to apply a bias voltage to the source electrodes of all transistors during the occurrence of a sampling potential, means to pas a source-drain current through those transistors having a conducting channel formed therein in response to a bias voltage, means to detect the occurrence of a source-drain current in a given transistor, and means to apply a restoring potential to the transistors in said selected row after the application of a sampling pulse, said restoring potential having an amplitude that is equal and opposite to that of said sampling potential.

Claim 3

The memory circuit of claim 1 wherein said transistors are P-type enhancement transistors and wherein said first and second thresholds are positively and negatively polarized respectively.

Claim 4

The memory circuit of claim 2 wherein the means to set all of said transistors to a positive threshold includes a word line corresponding to each row of memory elements, said word line being connected directly to the gate electrode of each transistor in the corresponding row and capacitively coupled to the drain electrodes of the same transistors, a bit line corresponding to each column of memory elements, said bit line being connected to the source electrode of each transistor in the corresponding column, a substrate line connected to the common substrate, and means to apply a negative potential to said bit and substrate lines while holding said word lines at ground potential.

Claim 5

The memory circuit of claim 3 wherein the means to set selected transistors to a negative threshold includes means to set a word line containing the selected transistors to a negative potential while holding the substrate at ground potential, said means to set selected transistors to a negative threshold further including means to set those bit lines corresponding to columns containing a selected transistor at ground potential while holding the bit columns at a negative potential less than the potential of said word line.

Claim 6

The memory circuit of claim 4 wherein the means to apply a sampling potential includes means to drive a selected word line to a negative potential having a magnitude less than the potential used to set transistors to a threshold while holding the substrate lead at ground potential.

Claim 7

A digital memory circuit comprising an array of rows and columns of memory elements formed on a common substrate, each of said memory elements including a variable threshold insulated gate field effect transistor having drain and source electrodes and a gate electrode separated from the substrate by a gate insulator, means to apply a first positive potential across the gate insulator of each transistor in the array whereby each transistor is set to its positive threshold, means to apply a first negative potential across the gate insulators of selected transistors in said array in accordance with information to be stored whereby the selected transistors are set to their negative threshold value, readout means in said memory circuit, said readout means including sampling means to apply a sampling voltage to any selected row of memory elements, said sampling means including means to apply a second negative voltage across the gate insulator of the transistors in said selected row, said second negative voltage having a magnitude less than said first negative voltage, said sampling means further including means to apply a negative bias voltage to all bit lines in said memory circuit during the application of said second negative voltage whereby a current will be caused to flow in the bit lines connected to those transistors that are set to their positive threshold, and restoring means in said readout means for applying a restoring potential across the gate insulator of the transistors in said selected row of memory elements, said restoring potential having a magnitude equal and opposite to that of the sampling voltage.

Claim 8

A digital memory circuit comprising an array of rows and columns of memory elements formed on a common substrate, each of said memory elements including a variable threshold insulated gate field effect transistor having drain and source electrodes and a gate electrode separated from the substrate by a gate insulator, means to apply a first positive potential across the gate insulator of each transistor in the array whereby each transistor is set to its positive threshold, means to apply a first negative potential across the gate insulators of selected transistors in said array in accordance with information to be stored whereby the selected transistors are set to their negative threshold value, readout means in said memory circuit, said readout means including sampling means to apply a sampling voltage to any selected row of memory elements, said sampling means including means to apply a second negative voltage across the gate insulator of the transistors in said selected row, said second negative voltage having a magnitude less than said first negative voltage, said sampling means further including means to apply a negative bias voltage to all bit lines in said memory circuit during the application of said second negative voltage whereby a current will be caused to flow in the bit lines connected to those transistors that are set to their positive threshold, and restoring means in said readout means for applying a restoring potential across the gate insulator of the transistors in said selected row of memory elements, said restoring potential having a magnitude equal and opposite to that of the sampling voltage.