Patent US4825409A successfully refreshed from Google Patents.
US4825409A
Expired / Lapsed
US
⏱️ 0.0 years remaining
NMOS data storage cell for clocked shift register applications
Assignee: Amiga Development LLC
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Filing: 1985-05-13
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Granted: 1989-04-25
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Expires: 2005-05-13
Abstract
Abstract An improved NMOS storage cell for use in shift registers is disclosed. Among other components, it contains a pair of inverters--one them an enabling inverter. A pre-charge transistor is placed in parallel with the first inverter to decrease the rise time associated with the transition from a logic low level output to a logic high level output. The result of adding the pre-charge transistor to the circuit is to increase the speed of operation of the storage cell, without the accompanying decrease in density with prior art methods, where the components must be enlarged. Another aspect of the present invention which further increases the density of the cell is the elimination of the complement clock line found in many prior art storage cells. The previous combination of a second inverter and a pass transistor connected to a complement clock line, is replaced by an enabling inverter connected to the clock line.
Inventors
- 👤 Jeffrey M. Bessolo
- 👤 Michael A. Wolf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:02
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/35606; G; G11; G11C; G11C19/00; G11C19/28; H03K3/356086; H03K3/356095
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
190 words
A NMOS data storage cell comprising: clocking means input for inputting a single timing signal; data input means for inputting data to said data storage cell; a pre-charge transistor connected at its gate to said clocking means input, for pre-charging the output of said storage cell to the logic high level voltage when said timing signal is a logic high level voltage; a first pass transistor connected to said clocking means input, to allow the input of data from said data input means when said clocking means input signal is at a logic high level and to prevent the input of data when said clocking means input signal is at a logic low level; a first inverter connected to said first pass transistor and to the output of said data storage cell, for inverting input data received at the input of said inverter from said first pass transistor; and a second inverter connected at its input to the output of said data storage cell and at its output to the input of said first inverter, for inverting data received at its input from the output of said data storage cell.
Claim 2
Dependent Claim
190 words
A NMOS data storage cell comprising: clocking means input for inputting a single timing signal; data input means for inputting data to said data storage cell; a pre-charge transistor connected at its gate to said clocking means input, for pre-charging the output of said storage cell to the logic high level voltage when said timing signal is a logic high level voltage; a first pass transistor connected to said clocking means input, to allow the input of data from said data input means when said clocking means input signal is at a logic high level and to prevent the input of data when said clocking means input signal is at a logic low level; a first inverter connected to said first pass transistor and to the output of said data storage cell, for inverting input data received at the input of said inverter from said first pass transistor; and a second inverter connected at its input to the output of said data storage cell and at its output to the input of said first inverter, for inverting data received at its input from the output of said data storage cell.
Claim 3
Dependent Claim
218 words
A NMOS data storage cell comprising: clocking means input for inputting a single timing signal; data input means for inputting data to said data storage cell; a first pass transistor connected to said clocking means input, to allow the input of data from said data input means when said clocking means input signal is at a logic high level and to prevent the input of data when said clocking means input signal is at a logic low level; a first inverter connected to said first pass transistor and to the output of said data storage cell, for inverting input data received at the input of said inverter from said first pass transistor; and a second inverter connected at its input to the output of said data storage cell and at its output to the input of said first inverter, for inverting data received at its input from the output of said data storage cell, said second inverter including a transistor pair having the source of one of the pair connected to said clocking means input signal, so that said second inverter is enabled to pass data when said clocking means input signal is at a logic low level, and is disabled to prevent the passage of data when said clock input signal is at a logic high level.
Claim 4
Dependent Claim
218 words
A NMOS data storage cell comprising: clocking means input for inputting a single timing signal; data input means for inputting data to said data storage cell; a first pass transistor connected to said clocking means input, to allow the input of data from said data input means when said clocking means input signal is at a logic high level and to prevent the input of data when said clocking means input signal is at a logic low level; a first inverter connected to said first pass transistor and to the output of said data storage cell, for inverting input data received at the input of said inverter from said first pass transistor; and a second inverter connected at its input to the output of said data storage cell and at its output to the input of said first inverter, for inverting data received at its input from the output of said data storage cell, said second inverter including a transistor pair having the source of one of the pair connected to said clocking means input signal, so that said second inverter is enabled to pass data when said clocking means input signal is at a logic low level, and is disabled to prevent the passage of data when said clock input signal is at a logic high level.
Claim 5
Dependent Claim
252 words
A NMOS data storage cell comprising: clocking means input for inputting a single timing signal; data input means for inputting data to said data storage cell; a pre-charge transistor connected at its gate to said clocking means input, for pre-charging the output of said storage cell to the logic high level voltage when said timing signal is a logic high level voltage; a first pass transistor connected to said clocking means input, to allow the input of data from said data input means when said clocking means input signal is at a logic high level and to prevent the input of data when said clocking means input signal is at a logic low level; a first inverter connected to said first pass transistor and to the output of said data storage cell, for inverting input data received at the input of said inverter from said first pass transistor; and a second inverter connected at its input to the output of said data storage cell and at its output to the input of said first inverter, for inverting data received at its input from the output of said data storage cell, said second inverter including a transistor pair having the source of one of its transistors connected to said clock input signal, so that said second inverter is enabled to pass data when said clock input signal is at a logic low level, and is disabled to prevent the passage of data when said clock input signal is at a logic high level.
Claim 6
Dependent Claim
252 words
A NMOS data storage cell comprising: clocking means input for inputting a single timing signal; data input means for inputting data to said data storage cell; a pre-charge transistor connected at its gate to said clocking means input, for pre-charging the output of said storage cell to the logic high level voltage when said timing signal is a logic high level voltage; a first pass transistor connected to said clocking means input, to allow the input of data from said data input means when said clocking means input signal is at a logic high level and to prevent the input of data when said clocking means input signal is at a logic low level; a first inverter connected to said first pass transistor and to the output of said data storage cell, for inverting input data received at the input of said inverter from said first pass transistor; and a second inverter connected at its input to the output of said data storage cell and at its output to the input of said first inverter, for inverting data received at its input from the output of said data storage cell, said second inverter including a transistor pair having the source of one of its transistors connected to said clock input signal, so that said second inverter is enabled to pass data when said clock input signal is at a logic low level, and is disabled to prevent the passage of data when said clock input signal is at a logic high level.
Claim 7
Dependent Claim
20 words
A shift register for unidirectional propagation of data comprising a plurality of the NMOS data storage cell in claim 1.
Claim 8
Dependent Claim
20 words
A shift register for unidirectional propagation of data comprising a plurality of the NMOS data storage cell in claim 2.
Claim 9
Dependent Claim
20 words
A shift register for unidirectional propagation of data comprising a plurality of the NMOS data storage cell in claim 3.
Claim 10
Independent Claim
229 words
A method of storing binary data in a NMOS data storage cell comprising: inputting a single clocked timing signal; inputting data to be stored; pre-charging the output of said storage cell to the logic high level voltage when said clocked timing signal is at a logic high level voltage, using a pre-charge transistor having its gate coupled to the clocked timing signal; enabling a first pass transistor with said clocked timing signal, to allow the input of data when said clocked timing signal is at a logic high level; disabling said first pass transistor with said clocked timing signal, to prevent the input of data when said clocked timing signal is at a logic low level voltage; inverting the data inputted through said first pass transistor with a first inverter; inverting the output of said first inverter by a second inverter; coupling the output of said second inverter to the input of a second pass transistor having its gate coupled to the complement of said clocked timing signal; enabling said second pass transistor to allow the passage of data from said second inverter to said first inverter when said clocked timing signal is at a logic low level; and disabling said second pass transistor to prevent the passage of data from said second inverter to said first inverter when said clocked timing signal is at a logic high level.
Claim 11
Independent Claim
229 words
A method of storing binary data in a NMOS data storage cell comprising: inputting a single clocked timing signal; inputting data to be stored; pre-charging the output of said storage cell to the logic high level voltage when said clocked timing signal is at a logic high level voltage, using a pre-charge transistor having its gate coupled to the clocked timing signal; enabling a first pass transistor with said clocked timing signal, to allow the input of data when said clocked timing signal is at a logic high level; disabling said first pass transistor with said clocked timing signal, to prevent the input of data when said clocked timing signal is at a logic low level voltage; inverting the data inputted through said first pass transistor with a first inverter; inverting the output of said first inverter by a second inverter; coupling the output of said second inverter to the input of a second pass transistor having its gate coupled to the complement of said clocked timing signal; enabling said second pass transistor to allow the passage of data from said second inverter to said first inverter when said clocked timing signal is at a logic low level; and disabling said second pass transistor to prevent the passage of data from said second inverter to said first inverter when said clocked timing signal is at a logic high level.
Claim 12
Independent Claim
208 words
A method of storing binary data in a NMOS data storage cell comprising: inputting a single clocked timing signal; inputting data to be stored; enabling a first pass transistor with said clocked timing signal, to allow the input of data when said clocked timing signal is at a logic high level; disabling said first pass transistor with said clocked timing signal, to prevent the input of data when said clocked timing signal is at a logic low level voltage; inverting the data inputted through said first pass transistor with a first inverter; and coupling a second inverter at its input to the output of said data storage cell and at its output to the input of said first inverter, said second inverter including a transistor pair having the source of one of the pair connected to said clocked timing signal thereby enabling said second inverter to invert data received from the output of said first inverter, and passing said inverted data, when said clocked timing signal is at a logic low level, and disabling said second inverter to prevent data received from the output of said first inverter from being inverted and passed by said second inverter, when said clocked timing signal is at a logic high level.
Claim 13
Independent Claim
208 words
A method of storing binary data in a NMOS data storage cell comprising: inputting a single clocked timing signal; inputting data to be stored; enabling a first pass transistor with said clocked timing signal, to allow the input of data when said clocked timing signal is at a logic high level; disabling said first pass transistor with said clocked timing signal, to prevent the input of data when said clocked timing signal is at a logic low level voltage; inverting the data inputted through said first pass transistor with a first inverter; and coupling a second inverter at its input to the output of said data storage cell and at its output to the input of said first inverter, said second inverter including a transistor pair having the source of one of the pair connected to said clocked timing signal thereby enabling said second inverter to invert data received from the output of said first inverter, and passing said inverted data, when said clocked timing signal is at a logic low level, and disabling said second inverter to prevent data received from the output of said first inverter from being inverted and passed by said second inverter, when said clocked timing signal is at a logic high level.
Claim 14
Independent Claim
246 words
A method of storing binary data in a NMOS data storage cell comprising: inputting a single clocked timing signal; inputting data to be stored; pre-charging the output of said storage cell to the logic high level voltage when said clocked timing signal is at a logic high level voltage, using a pre-charge transistor having its gate coupled to the clocked timing signal; enabling a first pass transistor with said clocked timing signal, to allow the input of data when said clocked timing signal is at a logic high level; disabling said first pass transistor with said clocked timing signal, to prevent the input of data when said clocked timing signal is at a logic low level voltage; inverting the data inputted through said first pass transistor with a first inverter; and coupling a second inverter at its input to the output of said data storage cell and at its output to the input of said first inverter, said second inverter including a transistor pair having the source of one of the pair connected to said clocked timing signal, thereby enabling said second inverter to invert data received from the output of said first inverter, and passing said inverted data, when said clocked timing signal is at a logic low level, and disabling said second inverter to prevent data received from the output of said first inverter from being inverted and passed by said second inverter, when said clocked timing signal is at a logic high level.
Claim 15
Independent Claim
246 words
A method of storing binary data in a NMOS data storage cell comprising: inputting a single clocked timing signal; inputting data to be stored; pre-charging the output of said storage cell to the logic high level voltage when said clocked timing signal is at a logic high level voltage, using a pre-charge transistor having its gate coupled to the clocked timing signal; enabling a first pass transistor with said clocked timing signal, to allow the input of data when said clocked timing signal is at a logic high level; disabling said first pass transistor with said clocked timing signal, to prevent the input of data when said clocked timing signal is at a logic low level voltage; inverting the data inputted through said first pass transistor with a first inverter; and coupling a second inverter at its input to the output of said data storage cell and at its output to the input of said first inverter, said second inverter including a transistor pair having the source of one of the pair connected to said clocked timing signal, thereby enabling said second inverter to invert data received from the output of said first inverter, and passing said inverted data, when said clocked timing signal is at a logic low level, and disabling said second inverter to prevent data received from the output of said first inverter from being inverted and passed by said second inverter, when said clocked timing signal is at a logic high level.
Claim 16
Dependent Claim
87 words
The NMOS data storage cell of claim 1 wherein the output of said second inverter is connected to the input of said first inverter by means of a second pass transistor that is arranged to allow the passage of data from said second inverter to said first inverter when said clocking means input signal is at a logic low level, and to prevent the passage of data from said second inverter to said first inverter when said clocking means input signal is at a logic high level.
References Cited (Backward Citations)
US3389383A
Cited
US3662356A
Cited
US3831155A
Cited
US4062000A
Cited
US4112296A
Cited
US4499559A
Cited
US4380055A
Cited
US4458337A
Cited
US4542484A
Cited
US4409680A
Cited
US4607350A
Cited
US4559619A
Cited
US4558434A
Cited
US4598214A
Cited
US4654826A
Cited
US4651333A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-24 | 1992-10-24 | 1993-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-24 | 1996-10-24 | 1997-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-24 | 2000-10-24 | 2001-04-25 | $7700.00 | Window Closed / Lapsed |