Abstract A MOSFET random access memory having a highly sensitive sense amplifier is disclosed. The sense amplifier utilizes a field effect transistor connected in the common gate mode so as to produce a large output swing on a reltively low capacitance output node, which is the drain node of the transistor, as a result of a relatively low voltage swing produced by reading data stored in a memory cell on a high capacitance column bus connected to the source of the transistor. The sense amplifier is shown in differential configuration with a low power level shifting circuit and also with both static memory cells, where a greatly improved access time is produced, and with destructive readout cells where improved reliability is possible.
The method for reading data from a static memory cell of an integrated circuit memory having a d.c. current path from a sense bus to a source supply voltage means when addressed representing one logic state which comprises precharging the sense bus from a voltage source through a field effect transistor to a predetermined voltage level, then addressing the memory cell to initiate the d.c. current path, and detecting the current flow through the sense bus as an indication of the logic state of the cell before the voltage of the sense bus has been substantially reduced.
Claim 2
Independent Claim
97 words
The method for reading data from a static memory cell of an integrated circuit memory having a d.c. current path from a sense bus to a source supply voltage means when addressed representing one logic state which comprises precharging the sense bus from a voltage source through a field effect transistor to a predetermined voltage level, then addressing the memory cell to initiate the d.c. current path, and detecting the current flow through the sense bus as an indication of the logic state of the cell before the voltage of the sense bus has been substantially reduced.