US4607350A
Expired / Lapsed
US
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Static memory cell
Assignee: Siemens AG
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Filing: 1982-12-02
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Granted: 1986-08-19
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Expires: 2002-12-02
Abstract
Abstract Static memory cell, including two fed-back inverters each having a switching transistor having drain, source and gate electrodes, a load element in the form of a depletion transistor having drain, source and gate electrodes, an output node connected to the drain electrode of the switching transistor and the gate electrode of the depletion transistor, and an additional potential source connected between the output node and the source electrode of the depletion transistor.
Inventors
- 👤 Cosimo Scianna
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:44
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
94 words
Static memory cell, comprising a bistable multivibrator including two cross-coupled fed-back inverters each including a switching transistor having drain, source and gate electrodes, a load element in the form of a depletion transistor having drain, source and gate electrodes, a supply potential source connected to the drain electrode of said depletion transistor, an output node connected to the drain electrode of the switching transistor and the gate electrode of the depletion transistor, and an additional circuit element providing a voltage drop connected between said output node and the source electrode of said depletion transistor.
Claim 2
Dependent Claim
94 words
Static memory cell, comprising a bistable multivibrator including two cross-coupled fed-back inverters each including a switching transistor having drain, source and gate electrodes, a load element in the form of a depletion transistor having drain, source and gate electrodes, a supply potential source connected to the drain electrode of said depletion transistor, an output node connected to the drain electrode of the switching transistor and the gate electrode of the depletion transistor, and an additional circuit element providing a voltage drop connected between said output node and the source electrode of said depletion transistor.
Claim 3
Dependent Claim
22 words
Memory cell according to claim 1, wherein said additional circuit element is an enhancement transistor having gate and drain electrodes connected together.
Claim 4
Dependent Claim
84 words
Memory cell according to claim 2, wherein said enhancement transistor forms a voltage between the drain and source electrodes thereof in the range between V tEO and V x2Y , where: V tEO is the cutoff voltage of said enhancement transistor for a source voltage equal to zero; and ##EQU13## where ##EQU14## F D is the substrate control factor of a depletion transistor, φ F is the Fermi potential and V tDO is the cutoff voltage of said depletion transistor for source voltage 0.
Claim 5
Dependent Claim
30 words
Memory cell according to claim 1, wherein the gate electrode of each respective switching transistor is connected to the drain electrode of the other switching transistor forming said bistable multivibrator.
Claim 6
Dependent Claim
25 words
Memory cell according to claim 1 wherein the gate electrodes of the depletion transistors are negatively biased with respect to the source electrodes there of.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-18 | 1990-02-17 | 1990-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-18 | 1994-02-17 | 1994-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-18 | 1998-02-17 | 1998-08-19 | $7700.00 | Window Closed / Lapsed |