US4499559A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Static RAM with bit-line-charging transistor
Assignee: Fujitsu Ltd
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Filing: 1984-01-31
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Granted: 1985-02-12
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Expires: 2004-01-31
Abstract
Abstract A static RAM, including a bit-line-charging transistor connected, in parallel to the load transistor, between each bit line and the power supply. These bit-line-charging transistors are controlled by a control signal generator circuit, which provides a timed pulse to their gates at the conclusion of each write cycle. The width of this timed pulse is selected such that bit lines which have been driven to a low level (e.g., zero volts) during a write cycle are rapidly recharged to the low level (e.g., 2.5 volts) to which they might have been driven during a read cycle. Thus, reverse readout operations (e.g., where a "1" is read immediately after a "0" has been written) no longer pose an obstacle to improving read operation speed, and speed and density can be improved.
Inventors
- 👤 Setsuo Kurafuji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:06
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
233 words
A static RAM for performing read and write operations and operatively connectable to receive a write enable signal, comprising: a plurality of bit line pairs; a plurality of memory cells connected to each pair of said bit line pairs; a plurality of bit line load elements, one of which is connected to a respective one of said bit lines; a plurality of bit-line-charging transistors each having a gate, said plurality of bit-line-charging transistors respectively connected to corresponding ones of said bit lines so that each of said bit-line-charging transistors is connected between a power supply and the corresponding one of said bit lines; and means, connected to the respective gates of said respective bit-line-charging transistors and connected to receive the write enable signal, for providing a pulse signal whenever the write enable signal changes state at the end of each write operation, said means for providing a pulse signal comprising: a first inverter having an input connected to receive the write enable signal and having an output; a second inverter having an input connected to said output of said first inverter and having an output; a capacitor connected to said output of said second inverter; and a NOR gate having a first input connected to said output of said second inverter, having a second input connected to said output of said first inverter, and having an output connected to said respective bit-line-charging transistors.
Claim 2
Dependent Claim
233 words
A static RAM for performing read and write operations and operatively connectable to receive a write enable signal, comprising: a plurality of bit line pairs; a plurality of memory cells connected to each pair of said bit line pairs; a plurality of bit line load elements, one of which is connected to a respective one of said bit lines; a plurality of bit-line-charging transistors each having a gate, said plurality of bit-line-charging transistors respectively connected to corresponding ones of said bit lines so that each of said bit-line-charging transistors is connected between a power supply and the corresponding one of said bit lines; and means, connected to the respective gates of said respective bit-line-charging transistors and connected to receive the write enable signal, for providing a pulse signal whenever the write enable signal changes state at the end of each write operation, said means for providing a pulse signal comprising: a first inverter having an input connected to receive the write enable signal and having an output; a second inverter having an input connected to said output of said first inverter and having an output; a capacitor connected to said output of said second inverter; and a NOR gate having a first input connected to said output of said second inverter, having a second input connected to said output of said first inverter, and having an output connected to said respective bit-line-charging transistors.
Claim 3
Dependent Claim
29 words
A static RAM as set forth in claim 1, wherein each of said bit-line-charging transistors comprises a MOSFET, having a gate connected to the output of said NOR gate.
Claim 4
Dependent Claim
67 words
A static RAM as set forth in claim 2, further comprising word lines, wherein each of said memory cells includes first and second gate transistors both of which are controlled by a respective one of said word lines, said first and second gate transistors of each of said memory cells connected between said respective memory cells and corresponding ones of a corresponding pair of said bit lines.
Claim 5
Dependent Claim
47 words
A static RAM as set forth in claim 1 or 3, further comprising means, connected to respective pairs of said bit lines, for selectively driving said respective pairs of said bit lines, to write selected information into a selected memory cell connected to said selected bit lines.
Claim 6
Dependent Claim
28 words
A static RAM as set forth in claim 4, wherein said driving means drives one bit line of a selected pair of bit lines to approximately zero volts.
Claim 7
Dependent Claim
72 words
A static RAM as set forth in claim 5, wherein said pulse signal provided to said bit-line-charging transistors by said means for providing a pulse signal is of a duration such that a respective bit line having a voltage of approximately zero volts is charged by said corresponding bit-line-charging transistor, during said duration of said pulse signal, to an intermediate voltage level between zero volts and the voltage of the power supply.
Claim 8
Dependent Claim
76 words
A static RAM as set forth in claim 6, wherein each said memory cell selectively provides a high or low level voltage to respective ones of said pair of bit lines to which said respective memory cells are connected, and wherein said intermediate voltage level, to which said bit line is recharged by said bit-line-charging transistor, is approximately equal to said low level voltage provided to respective bit lines by respective ones of said memory cells.
Claim 9
Dependent Claim
214 words
A static RAM for performing read and write operations, comprising: a plurality of bit line pairs; a plurality of memory cells connected to each pair of said bit line pairs; a plurality of bit line load elements, one of which is connected to a respective one of said bit lines; a plurality of bit-line-charging transistors each having a gate, said plurality of bit-line-charging transistors respectively connected to corresponding ones of said bit lines; means, connected to the respective gates of said respective bit-line-charging transistors, for providing a pulse signal at the end of each write operation, said pulse signal provided to said bit-line-charging transistors by said means for providing a pulse signal, said pulse signal being of a duration such that a respective bit line having a voltage of approximately zero volts is charged by said corresponding bit-line-charging transistor during said duration of said pulse signal, to an intermediate voltage level between zero volts and the voltage of a power supply; and means, connected to respective pairs of said bit lines, for selectively driving said respective pairs of said bit lines to write selected information into a selected memory cell connected to said selected bit lines, said driving means driving one bit line of a selected pair of bit lines to approximately zero volts.
Claim 10
Dependent Claim
214 words
A static RAM for performing read and write operations, comprising: a plurality of bit line pairs; a plurality of memory cells connected to each pair of said bit line pairs; a plurality of bit line load elements, one of which is connected to a respective one of said bit lines; a plurality of bit-line-charging transistors each having a gate, said plurality of bit-line-charging transistors respectively connected to corresponding ones of said bit lines; means, connected to the respective gates of said respective bit-line-charging transistors, for providing a pulse signal at the end of each write operation, said pulse signal provided to said bit-line-charging transistors by said means for providing a pulse signal, said pulse signal being of a duration such that a respective bit line having a voltage of approximately zero volts is charged by said corresponding bit-line-charging transistor during said duration of said pulse signal, to an intermediate voltage level between zero volts and the voltage of a power supply; and means, connected to respective pairs of said bit lines, for selectively driving said respective pairs of said bit lines to write selected information into a selected memory cell connected to said selected bit lines, said driving means driving one bit line of a selected pair of bit lines to approximately zero volts.
Claim 11
Dependent Claim
76 words
A static RAM as set forth in claim 8, wherein each said memory cell selectively provides a high or low level voltage to respective ones of said pair of bit lines to which said respective memory cells are connected, and wherein said intermediate voltage level, to which said bit line is recharged by said bit-line-charging transistor, is approximately equal to said low level voltage provided to respective bit lines by respective ones of said memory cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-12 | 1988-08-13 | 1989-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-12 | 1992-08-13 | 1993-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-12 | 1996-08-13 | 1997-02-12 | $7700.00 | Window Closed / Lapsed |